P
RODUCT
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PECIFICATION
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Two Independent 0-to-10-mbps Full-Duplex Channels,
each with Two Baud Rate Generators and One Digital
Phase-Locked Loop for Clock Recovery
32-Byte Data FIFO’s for each Receiver and Transmitter
110-ns Bus Cycle Time, 16-Bit Data Bus Bandwidth
Multi-Protocol Operation under Program Control with
Independent Mode Selection for Receiver and Transmit-
ter
Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop
Bits/Character in 1/16-Bit Increments; Programmable
Clock Factor; Break Detect and Generation; Odd, Even,
Mark, Space or no Parity and Framing Error Detection;
Supports One Address/Data Bit and MIL STD 1553B
Protocols
Byte Oriented Synchronous Mode with One to Eight
Bits/Character; Programmable Idle Line Condition; Op-
tional Receive Sync Stripping; Optional Preamble
Transmission; 16- or 32-Bit CRC and Transmit-to-Re-
ceive Slaving (for X.21)
Bisync Mode with 2- to 16-Bit Programmable Sync
Character; Programmable Idle Line Condition; Optional
Receive Sync Stripping; Optional Preamble Transmis-
sion; 16- or 32-Bit CRC
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Transparent Bisync Mode with EBCDIC or ASCII Char-
acter Code; Automatic CRC Handling; Programmable
Idle Line Condition; Optional Preamble Transmission;
Automatic Recognition of DLE, SYN, SOH, ITX, ETX,
ETB, EOT, ENQ and ITB
External Character Sync Mode for Receive
HDLC/SDLC Mode with Eight-Bit Address Compare;
Extended Address Field Option; 16- or 32-Bit CRC; Pro-
grammable Idle Line Condition; Optional Preamble
Transmission and Loop Mode
DMA Interface with Separate Request and Acknowl-
edge for Each Receiver and Transmitter
Channel Load Command for DMA Controlled Initializa-
tion
Flexible Bus Interface for Direct Connection to Most
Microprocessors; User Programmable for 8 or 16 Bits
Wide. Directly Supports 680X0 Family or 8X86 Family
Bus Interfaces
Low Power CMOS
68-Pin PLCC/100-Pin VQFP Packages
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The Z16C30 USC™ Universal Serial Controller is a dual-
channel multi-protocol data communications peripheral de-
signed for use with any conventional multiplexed or non-
multiplexed bus. The USC functions as a serial-to-parallel,
parallel-to-serial converter/controller and may be software
configured to satisfy a wide variety of serial communica-
tions applications. The device contains a variety of new, so-
phisticated internal functions including two baud rate gen-
erators per channel, one digital phase-locked loop per
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channel, character counters for both receive and transmit in
each channel and 32-byte data FIFO’s for each receiver and
transmitter (Figure 1).
ZiLOG now offers a high speed version of the USC with
improved bus bandwidth. CPU bus accesses have been
shortened from 160 ns per access to 110 ns per access. The
USC has a transmit and receive clock range of up to 10 MHz
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(20 MHz when using the DPLL, BRG, or CTR) and data
transfer rates as high as 10 Mbits/sec full duplex.
The USC handles asynchronous formats, synchronous
byte-oriented formats such as BISYNC and synchronous
bit-oriented formats such as HDLC. This device supports
virtually any serial data transfer application.
The device can generate and check CRC in any synchronous
mode and can be programmed to check data integrity in var-
ious modes. The USC also has facilities for modem controls
in both channels. In applications where these controls are
not needed, the modem controls may be used for general-
purpose I/O. The same is true for most of the other pins in
each channel.
Interrupts are supported with a daisy-chain hierarchy, with
the two channels having completely separate interrupt
structures.
High-speed data transfers through DMA are supported by
a Request/Acknowledge signal pair for each receiver and
transmitter. The device supports automatic status transfer
through DMA and also allows device initialization under
DMA control.
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When written to, all reserved bits must be programmed
to 0.
To aid the designer in efficiently programming the USC,
support tools are available. The Technical Manual describes
in detail all features presented in this Product Specification
and gives programming sequence hints. The Programmer’s
Assistant is a MS-DOS disk-based programming initializa-
tion tool to be used in conjunction with the Technical Man-
ual. There are also available assorted application notes and
development boards to assist the designer in the hard-
ware/software development.
All Signals with an overline, are active Low. For example:
B/W, in which WORD is active Low, and B/W, in which
BYTE is active Low.
Power connections follow these conventional descriptions:
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