UPD44321362F1-A50Y-FQ2 datasheet, PDF

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UPD44321362F1-A50Y-FQ2: DescriptionZBT SRAM, 1MX36, 3.2ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165; Categorystorage storage; File Size749KB，40 Pages; ManufacturerNEC Electronics

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UPD44321362F1-A50Y-FQ2 Overview

ZBT SRAM, 1MX36, 3.2ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, FBGA-165

UPD44321362F1-A50Y-FQ2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	3.2 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	37748736 bi
Memory IC Type	ZBT SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD44321182, 44321322, 44321362

32M-BIT ZEROSB

SRAM

PIPELINED OPERATION

Description

The

PD44321182 is a 2,097,152-word by 18-bit, the

PD44321322 is a 1,048,576-word by 32-bit and the

PD44321362 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using

full CMOS six-transistor memory cell.

The

PD44321182,

PD44321322 and

PD44321362 are optimized to eliminate dead cycles for read to write, or

write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst

counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single

clock input (CLK).

The

PD44321182,

PD44321322 and

PD44321362 are suitable for applications which require synchronous

operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).

In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal

operation.

The

PD44321182,

PD44321322 and

PD44321362 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm

package thickness or 165-pin PLASTIC FBGA for high density and low capacitive loading.

Features

•

Low voltage core supply : V

= 3.3 ± 0.165V (-A44, -A50, -A60, -A44Y, -A50Y, -A60Y)

= 2.5 ± 0.125V (-C50, -C60, -C50Y, -C60Y)

•

Synchronous operation

•

Operating temperature : T

= 0 to 70 °C (-A44, -A50, -A60, -C50, -C60)

= –40 to +85 °C (-A44Y, -A50Y, -A60Y, -C50Y, -C60Y)

•

100 percent bus utilization

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

All registers triggered off positive clock edge

•

3.3V or 2.5V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 to /BW4 (

PD44321322 and

PD44321362)

/BW1 and /BW2 (

PD44321182)

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with NEC Electronics sales

representative for availability and additional information.

Document No. M16024EJ1V0DS00 (1st edition)

Date Published December 2002 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2002

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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