UPD4442183GF-A44 datasheet, PDF

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UPD4442183GF-A44: DescriptionCache SRAM, 256KX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100; Categorystorage storage; File Size210KB，28 Pages; ManufacturerNEC Electronics

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UPD4442183GF-A44 Overview

Cache SRAM, 256KX18, 2.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

UPD4442183GF-A44 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NEC Electronics
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compli
ECCN code	3A991.B.2.A

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD4442163, 4442183, 4442323, 4442363

4M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

DOUBLE CYCLE DESELECT

Description

The

PD4442163 is a 262,144-word by 16-bit, the

PD4442183 is a 262,144-word by 18-bit,

PD4442323 is a

131,072-word by 32-bit and the

PD4442363 is a 131,072-word by 36-bit synchronous static RAM fabricated with

advanced CMOS technology using Full-CMOS six-transistor memory cell.

The

PD4442163,

PD4442183,

PD4442323 and

PD4442363 integrates unique synchronous peripheral circuitry,

2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The

PD4442163,

PD4442183,

PD4442323 and

PD4442363 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer

memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The

PD4442163,

PD4442183,

PD4442323 and

PD4442363 are packaged in 100-pin PLASTIC LQFP with a

1.4 mm package thickness for high density and low capacitive loading.

Features

•

3.3 V power supply

•

Synchronous operation

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

Double-Cycle deselect timing

•

All registers triggered off positive clock edge

•

3.3 V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 2.5 ns (250 MHz), 2.8 ns (225 MHz), 3.0 ns (200 MHz), 3.5 ns (167 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 - /BW4 (

PD4442323,

PD4442363), /BW1 - /BW2 (

PD4442163,

PD4442183), /BWE

Global write enable : /GW

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15394EJ1V0DS00 (1st edition)

Date Published May 2001 NS CP(K)

Printed in Japan

2001

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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