7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
w/Zo=100ohms
9DBU0741
DATASHEET
Description
The 9DBU0741 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100 transmission lines. The device has 7
output enables for clock management, and 3 selectable
SMBus addresses.
Features/Benefits
•
Integrated terminations; save 28 resistors compared to
•
•
•
•
•
•
standard HCSL outputs
36mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
•
slew rate for each output
•
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
Recommended Application
1.5V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
•
7 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
•
•
•
•
DIF
additive
cycle-to-cycle jitter <5ps
DIF output-to-output skew < 60ps
DIF
additive
phase jitter is <300fs rms for PCIe Gen3
DIF
additive
phase jitter <350s rms for SGMII
•
•
•
•
Block Diagram
vOE(6:0)#
7
DIF6
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0741 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.
9DBU0741 DATASHEET
Pin Configuration
^CKPWRGD_PD#
40 39 38 37 36 35 34 33 32 31
vSADR_tri
1
vOE6#
2
DIF6
3
DIF6#
4
VDDR1.5
5
CLK_IN
6
CLK_IN#
7
GNDDIG
8
SCLK_3.3
9
SDATA_3.3
10
11 12 13 14 15 16 17 18 19 20
VDDDIG1.5
DIF0#
vOE0#
VDD1.5
VDDIO
VDDIO
DIF1#
DIF0
DIF1
NC
30
NC
29
vOE3#
28
DIF3#
27
DIF3
9DBU0741
epad is GND
VDD1.5
26
VDDIO
25
VDDA1.5
24
vOE2#
23
DIF2#
22
DIF2
21
vOE1#
VDDIO
40-VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
0
1
1
1
CLK_IN
X
Running
Running
Running
SMBus
OEx bit
X
0
1
1
OEx# Pin
X
X
0
1
DIFx
True O/P Comp. O/P
Low
Low
Low
Low
Running
Running
Low
Low
Power Connections
Pin Number
VDD
5
11
16,25,31
12,17,26,32,
39
VDDIO
GND
41
8
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
2
VDDIO
vOE5#
vOE4#
DIF5#
DIF4#
DIF5
DIF4
REVISION C 04/22/15
9DBU0741 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PIN NAME
vSADR_tri
vOE6#
DIF6
DIF6#
VDDR1.5
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.5
VDDIO
vOE0#
DIF0
DIF0#
VDD1.5
VDDIO
DIF1
DIF1#
NC
vOE1#
DIF2
DIF2#
vOE2#
VDDA1.5
VDDIO
DIF3
DIF3#
vOE3#
NC
VDD1.5
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
ePAD
PIN
TYPE
DESCRIPTION
LATCHE Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
D IN
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
1.5V power for differential input clock (receiver). This VDD should be treated as an
PWR
Analog power rail and filtered appropriately.
IN
True Input for differential reference clock.
IN
Complementary Input for differential reference clock.
GND
Ground pin for digital circuitry
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
PWR
1.5V digital power (dirty power)
PWR
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
PWR
Power supply, nominally 1.5V
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
N/A
No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
1.5V power for the PLL core.
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
N/A
No Connection.
PWR
Power supply, nominally 1.5V
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low
IN
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal pull-up resistor.
GND
Connect paddle to ground.
REVISION C 04/22/15
3
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
9DBU0741 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100
2pF
2pF
Rs
Note: The device can drive transmission line lengths greater
than those allowed by the PCIe SIG
Driving LVDS
3.3V
Driving LVDS
Cc
R7a
R7b
Rs
Zo
Cc
R8a
Rs
Device
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
termination
have termination Note
10K ohm
140 ohm
5.6K ohm
75 ohm
0.1 uF
0.1 uF
1.2 volts
1.2 volts
Component
R7a, R7b
R8a, R8b
Cc
Vcm
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
4
REVISION C 04/22/15
9DBU0741 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBU0741. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to VDD, VDDA and VDDIO
SMBus clock and data pins
MIN
-0.5
-0.5
-65
TYP
MAX
2
V
DD
+0.5
3.3
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1,
1
1
1
1
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.0V.
Electrical Characteristics–Clock Input Parameters
TA = T
AMB,
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Input Common Mode
Voltage - DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
V
COM
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
CONDITIONS
Common Mode Input Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential wavefrom
Differential Measurement
MIN
200
300
0.4
-5
45
0
TYP
MAX
725
1450
8
5
55
150
UNITS NOTES
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
50
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
REVISION C 04/22/15
5
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
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