REVISIONS
LTR
A
B
C
D
E
F
DESCRIPTION
Added changes in accordance with NOR 5962-R116-94.
Added 03 device, removed CAGE number 01295, and made editorial
changes throughout.
Added changes in accordance with NOR 5962-R059-97.
Added changes in accordance with NOR 5962-R193-97.
Corrected radiation circuit. Updated boilerplate. ksr
Add 04 and 05 devices, change case outlines from CQCC2-F172 to
figure 4. Page 3, section 1.3 changed T
J
from 175°C to 150°C.
Added appendix A for die. Added CQFP package option case U, and
binning circuitry delay for 04 and 05 in Table IA. ksr
Change the generic number for the 01 and 02 devices as well as the
bin speed. Update the binning circuit delay on table IA. Update the
bin speed for the 01 device in section 10.2.2. ksr
Replaced figure 1, case outline Y with new graphic art work. ksr
Boilerplate update, part of 5 year review. ksr
DATE (YR-MO-DA)
94-03-03
96-07-09
96-11-12
97-03-03
98-03-31
98-09-18
APPROVED
M. A. Frye
M. A. Frye
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
G
98-11-15
Raymond Monnin
H
J
00-04-28
07-05-28
Raymond Monnin
Robert M. Heber
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
J
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REV
SHEET
PREPARED BY
Rajesh Pithadia
CHECKED BY
Jeff Bowling
APPROVED BY
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
Michael A. Frye
DRAWING APPROVAL DATE
93-04-07
REVISION LEVEL
J
J
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J
20
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21
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1
J
22
J
2
J
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3
J
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J
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STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
MICROCIRCUIT, MEMORY, DIGITAL,
CMOS, FIELD PROGRAMMABLE GATE
ARRAY, 8000 GATES, MONOLITHIC
SILICON
SIZE
CAGE CODE
A
SHEET
67268
1 OF
32
5962-92156
DSCC FORM 2233
APR 97
5962-E317-07
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
│
│
│
Federal
stock class
designator
\
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
03
04
05
Generic number
1280A
1280A-1
RH1280
1280XL
1280XL-1
Circuit function
8000 gate field programmable gate array
8000 gate field programmable gate array
8000 gate field programmable gate array
8000 gate field programmable gate array
8000 gate field programmable gate array
Bin speed
200 ns
170 ns
160 ns
120 ns
102 ns
-
│
│
│
RHA
designator
(see 1.2.1)
92156
01
│
│
│
Device
type
(see 1.2.2)
/
Q
│
│
│
Device
class
designator
(see 1.2.3)
Y
│
│
│
Case
outline
(see 1.2.4)
C
│
│
│
Lead
finish
(see 1.2.5)
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level
as follows:
Device class
M
Q or V
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN
class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Y
Z
U
Descriptive designator
CMGA7 - P176
See figure 1
CMGA7 - P176
See figure 1
Terminals
176
172
177
172
Package style
Pin grid array
Quad flat pack
Pin grid array with orientation pin
Quad flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-92156
SHEET
J
2
1.3 Absolute maximum ratings. 1/
DC supply voltage range (V
CC
) ..................................................................... -0.5 V dc to +7.0 V dc
Input voltage range (V
I
) ................................................................................ -0.5 V dc to V
CC
+ 0.5 V dc
Output voltage range (V
O
) ............................................................................ -0.5 V dc to V
CC
+ 0.5 V dc
Input clamp current (I
IC
) ................................................................................ ±20 mA
Output clamp current (I
OC
) ............................................................................ ±20 mA
Continuous output current (I
O
) ...................................................................... ±25 mA
Storage temperature range (T
STG
) ................................................................ -65°C to +150°C
Lead temperature (soldering, 10 seconds) ................................................... 300°C
Thermal resistance, junction-to-case (Θ
JC
) :
Case X and Z.............................................................................................. See MIL-STD-1835
Case Y and U ............................................................................................. 10°C/W 2/
Maximum junction temperature (T
J
).............................................................. +150°C
1.4 Recommended operating conditions.
Supply voltage (V
CC
) ..................................................................................... +4.5 V dc to +5.5 V dc
Case operating temperature range (T
C
)........................................................ -55°C to +125°C
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) ............................................. 100 percent 3/
1.6 Radiation features
Maximum total dose available (dose rate = 50 - 300 rads(Si)/s) .......................... 300K rads(Si)
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 -
MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
4/
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 -
MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at
http://assist.daps.dla.mil/quicksearch/
or
http://assist.daps.dla.mil
from the
Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ When the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated
herein.
3/ 100 percent test coverage of blank programmable logic devices.
4/ Device electrical characteristics are guaranteed for post irradiation levels at 25°C, in low dose rate environment (post 168
hours, 100°C, biased anneal).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-92156
SHEET
J
3
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of these documents are those cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192-00
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to:
ASTM International, PO Box C700, 100 Barr
Harbor Drive, West Conshohocken, PA 19428-2959;
http://www.astm.org.)
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78
-
IC Latch-Up Test.
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201;
http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute the
documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless
a specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 and figure 1 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s).
3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered
item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A,
B, C, D, or E (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of
the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered
item drawing pattern.
3.2.3.2 Programmed devices. The truth table or test vectors for programmed devices shall be as specified by an attached
altered item drawing.
3.2.4 Switching test circuit and waveforms . The switching test circuit and waveforms diagram shall be as specified on figure
3.
3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full
case operating temperature range.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
A
REVISION LEVEL
5962-92156
SHEET
J
4
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/
4.5 V < V
CC
< 5.5 V
-55°C < T
C
< +125°C
unless otherwise specified
Test one output at a time,
V
CC
= 4.5 V, I
OH
= -3.2 mA
Test one output at a time,
V
CC
= 4.5 V, I
OL
= 4.0 mA
Group A
Subgroups
Device
type
Min
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
All
All
All
01,02,
04,05
03
Standby supply current
I
DD
Outputs unloaded,
V
CC
= 5.5 V,
V
IN
= V
CC
or GND
V
CC
= 5.5 V,
V
IN
= V
CC
or GND
V
CC
= 5.5 V,
V
O
= V
CC
or GND
See 4.4.1c, f= 1.0 Mhz,
V
OUT
= 0 V
See 4.4.1e, V
O
= 0 V,
V
CC
= 4.5 V
See figure 3, V
IL
= 0 V,
V
IH
= 3.0 V, V
CC
= 4.5 V,
V
OUT
= 1.5 V 3/
1, 2, 3
All
-0.3
2.0
2.2
3.7
0.4
0.8
V
CC
+0.3
V
CC
+0.3
25
mA
Limits
Max
V
V
V
V
Unit
High Level output voltage
Low level output voltage
Low level input voltage
High level input voltage
V
OH
V
OL
V
IL
V
IH
Input leakage current
Output leakage current
I/O terminal capacitance
Functional tests
Binning circuit delay
I
IL
I
OZ
C
I/O
FT 2/
t
PBLH,
t
PBHL
1, 2, 3
1, 2, 3
4
7, 8A, 8B
9, 10, 11
All
All
All
All
-10
-10
10
10
20
µA
µA
pF
01
02
03
04
05
200
170
160
120
102
ns
1/
2/
3/
All tests shall be performed under the worst case condition unless otherwise specified. Devices supplied to this drawing will
meet levels M, D, L, R, and F, of irradiation. However, this device is only tested at the "F" level. Pre and post irradiation
values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for
any RHA level, T
A
= +25°C.
Devices are functionally tested using a serial scan test method. Data is shifted into the SDI pin and the DCLK pin is used
as a clock. The data is used to drive the inputs of the internal logic and I/O modules, allowing a complete functional test to
be performed. The outputs of the module can be read by shifting out the output response or by monitoring the PRA, PRB,
or SDO pins. These tests form a part of the manufacturer's test tape and shall be maintained and available at the approved
source(s) of supply upon request by DSCC or the OEM.
Binning circuit delay is defined as the input-to-output delay of a special path called the "binning circuit". The binning circuit
consists of one input buffer plus 16 combinatorial logic modules plus one output buffer. The logic modules are distributed
along the left side of the device. These modules are configured as non-inverting buffers and are connected through
programmed antifuses with typical capacitive loading.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-92156
SHEET
J
5
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