Standard Products
UT8QNF8M8 64Mbit NOR Flash Memory
Advanced Data Sheet
December 16, 2011
FEATURES
64Mbits organized as either 8M x 8-bits or 4M x16-bits
Fast 60ns read/write access time
Functionally compatible with traditional single power
supply Flash devices
Simultaneous read/write operations
Flexible bank architecture
Single 3.3V power supply
Ultra low power consumption
Near zero power standby operation
Full HiRel temperature range (-55
o
C to 105
o
C)
Data retention > 20 years @55
o
C
Programming Endurance: 10k cycles per sector
48-pin ceramic flatpack package
Operational environment:
- Total dose: 10, 30 or 50 krad(Si)
- SEL Immune: 80 MeV-cm
2
/mg @ 85
o
C
- SEU Immune: Memory Cell 100 MeV-cm
2
/mg @25
o
C
Standard Microelectronic Drawing (SMD), 5962-12204
- QML Q and Q+ pending
INTRODUCTION
The Aeroflex 64Mbit, 3.3 volt-only flash memory device, can
be organized as 4,194,304 words of 16-bits each or 8,388,608
bytes of 8-bits each. Word mode data appears on DQ[15:0];
byte mode data appears on DQ[7:0]. The device is designed to
be programmed in-system with the standard 3.3 volt VCC
supply and can also be programmed in standard PROM
programmers. The device is available with an access time of
60 ns and is offered in a 48-pin ceramic flatpack package.
Standard control pins—Chip Enable (CE#), Write Enable
(WE#), and Output Enable (OE#)—control normal read and
write operations, and avoid bus contention issues. The device
operates from a single 3.3 volt power supply.
APPLICATION
The UT8QNF8M8 64Mbit Flash Memory is compatible for use
with the UT699 LEON 3FT microprocessor. In a typical
application, the microprocessor transfers an image of the
application program or kernel from non-volatile memory, such
as flash, to volatile memory, such as SRAM. The Aeroflex
64Mbit NOR Flash is intended to provide customers with a non-
volatile solution that has a memory capacity large enough to
house a typical application program or kernel.
Figure 1. UT8QNF8M8 Flash Block Diagram
1
48-Lead Flatpack
Top View
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
Table 1. Pin Descriptions
SIGNAL
A[21:0]
DQ[14:0]
DQ15/A-1
CE#
OE#
WE#
WP#
RESET#
BYTE#
RY/BY#
V
CC
V
SS
22 Address pins
15 Data Inputs/Outputs, (x16-mode only)
DQ15 (Data Input/Output, word mode), A-1 (LSB
Address Input, byte mode)
Chip Enable, Active Low
Output Enable, Active Low
Write Enable, Active Low
Hardware Write Protect
Hardware reset pin, Active Low
Select 8-bit or 16-bit mode, Active Low
Ready/Busy Output, Active Low
3.3 volt only single power supply (see supply
tolerances)
Device Ground
FUNCTION
Figure 2. UT8QNF8M8 Pinout (48)
2
SIMULTANEOUS READ/WRITE OPERATIONS WITH
ZERO LATENCY
The Simultaneous Read/Write architecture provides simultane-
ous operation by dividing the memory space into four banks, two
8 Mb banks with small and large sectors, and two 24 Mb banks
of large sectors. Sector addresses are fixed, system software can
be used to form user-defined bank groups.
During an Erase/Program operation, any of the three non-busy
banks may be read from. Note that only two banks can operate
simultaneously. The device can improve overall system perfor-
mance by allowing a host system to program or erase in one
bank, then immediately and simultaneously read from the other
bank, with zero latency. This releases the system from waiting
for the completion of program or erase operations.
The UT8QNF8M8 is organized as a dual boot device with both
top and bottom boot sectors.
Table 2. Bank Architecture
Bank 1
Bank 2
Bank 3
Bank 4
8 Mb
24 Mb
24 Mb
8 Mb
Eight 8 kbyte/4 kword,
Fifteen 64 kybte/32 word
Forty-eight 64 kbyte/32 kword
Forty-eight 64 kbyte/32 kword
Eight 8 kbyte/4 kword,
Fifteen 64 kbyte/32 kword
3
UT8QNF8M8 FEATURES
The device offers complete compatibility with the JEDEC 42.4
single-power-supply Flash command set standard. Commands
are written to the command register using standard micropro-
cessor write timings. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
The host system can detect whether a program or erase opera-
tion is complete by using the device status bits: RY/BY# pin,
DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a pro-
gram or erase cycle has been completed, the device automati-
cally returns to the read mode.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents of
other sectors. The device is fully erased when shipped from the
factory.
Hardware data protection measures include a low VCC detector
that automatically inhibits write operations during power tran-
sitions. The hardware sector protection feature disables both
program and erase operations in any combination of the sectors
of memory.
The Erase Suspend/Erase Resume feature enables the user to
put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True
background erase can thus be achieved.
The device offers two power-saving features. When addresses
have been stable for a specified amount of time, the device en-
ters the automatic sleep mode. The system can also place the
deviceinto the standby mode. Power consumption is greatly re-
duced in both modes.
4
DEVICE BUS OPERATION
This section describes the requirements and use of the device
bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is a
latch used to store the commands, along with the address and
data information needed to execute the command. The
contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of
the device. Table 3 lists the device bus operations, the inputs
and control levels they require, and the resulting output.
Table 3. UT8QNF8M8 Device Bus Operations
DQ[15:8]
OPERATION
Read
Write
Standby
Output Disable
Reset
CE#
L
L
V
CC
+
0.3V
L
X
OE#
L
H
X
H
X
H
L
X
H
X
RESET#
H
H
V
CC
+
0.3V
H
L
WP#
L/H
(Note 2)
L/H
L/H
L/H
Addresses
A
IN
A
IN
X
X
X
1
BYTE#
= V
IH
D
OUT
D
IN
High-Z
High-Z
High-Z
BYTE# = V
IL
DQ[14:8] = High-Z,
DQ15 = A-1
High-Z
High-Z
High-Z
DQ[7:0]
D
OUT
D
IN
High-Z
High-Z
High-Z
Notes:
1. Addresses are A21:A0 in word mode (BYTE# = VIH), A21:A-1 in byte mode (BYTE# = VIL).
2. If WP# = VIL, sectors 0, 1, 140, and 141 remain protected. If WP# = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last
protected or unprotected.
5
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