MITSUMI
System Reset PST92XX
System Reset
Monolithic IC PST92XX Series
Outline
This reset IC in an ultra-compact package provides highly accurate detection and includes a delay circuit.
Features
1. Delay circuit
2. High detection accuracy
3. Low consumption current
delay time can be set through an external capacitor.
Vs±1.5%.
3µA typ.
Package
SOT-25
Applications
Microcomputer reset and detection of remaining battery charge.
Pin Assignment
1
5
4
2
3
1
2
3
4
5
SOT-25
(TOP VIEW)
TC
SUB
GND
V
OUT
V
CC
Equivalent Circuit Diagram
MITSUMI
System Reset PST92XX
Pin Description
Pin No.
Pin name
1
TC
2
SUB
3
GND
4
V
OUT
5
V
CC
Note 1 : Connect to GND.
Functions
T
PLH
control pin
Substrate pin
*
1
GND pin
Reset signal output pin
V
CC
pin/voltage detect pin
Absolute Maximum Ratings
Item
Storage temperature
Operating temperature
Supply voltage
Allowable loss
Symbol
T
STG
T
OPR
V
CC
max.
Pd
Ratings
-40~+125
-20~+175
-0.3~+110
150
Unit
°C
°C
V
mW
Recommended Operating Conditions
Item
Operating temperature
Supply voltage
Symbol
T
OPR
V
CC
Ratings
-20~+75
-0.3~+10
Unit
°C
V
Electrical Characteristics
Item
Symbol
(Ta=25°C) (Except where noted otherwise, resistance unit is
Ω)
Measurement
circuit
Measurement conditions
PST9246
PST9245
PST9244
PST9243
PST9242
PST9241
PST9240
PST9239
PST9238
PST9237
PST9236
PST9235
PST9234
PST9233
PST9232
PST9231
PST9230
PST9229
PST9228
PST9227
PST9226
PST9225
PST9224
PST9223
PST9222
PST9221
PST9220
PST9219
Min.
4.531
4.432
4.334
4.235
4.137
4.038
3.940
3.841
3.743
3.644
3.546
3.447
3.349
3.250
3.152
3.053
2.955
2.856
2.758
2.659
2.561
2.462
2.364
2.265
2.167
2.068
1.970
1.871
Typ.
4.600
4.500
4.400
4.300
4.200
4.100
4.000
3.900
3.800
3.700
3.600
3.500
3.400
3.300
3.200
3.100
3.000
2.900
2.800
2.700
2.600
2.500
2.400
2.300
2.200
2.100
2.000
1.900
Max.
4.669
4.568
4.466
4.365
4.263
4.162
4.060
3.959
3.857
3.756
3.654
3.553
3.451
3.350
3.248
3.147
3.045
2.944
2.842
2.741
2.639
2.538
2.436
2.335
2.233
2.132
2.030
1.929
Unit
Detecting voltage
V
S
1
V
CC
=H L
R
L
=4.7k
V
OL
< 0.4V
=
V
MITSUMI
System Reset PST92XX
Item
Hysteresis voltage
Symbol
Vs
Measurement
circuit
1
1
1
1
1
1
2
2
1
1
1
Measurement conditions
H L, R
L
=4.7k
S1 : ON
R
L
=4.7k, Ta=-20~+75°C
S1 : ON
V
CC
1=V
S
min. -0.05V
R
L
=4.7k S1 : ON
V
CC
1=V
CC
2=10V S2 : ON
V
CC
1=V
S
min. -0.05V R
L
=∞
V
CC
1=V
S
typ./0.85 R
L
=∞
R
L
=4.7k, C
L
=100pF
Cd=0.01µF
*
1
R
L
=4.7k, C
L
=100pF
Cd=0.01µF
*
2
R
L
=4.7k V
OL
< 0.4V S1 : ON
=
V
CC
1=V
S
min. -0.05V
V
CC
2=0.4V S2 : ON
V
CC
1=V
S
min. -0.05V
Ta=-20~+75°C S2 : ON
V
CC
1=L
Min.
25
Typ.
50
±0.01
0.1
5.0
3.0
(
*
3)
(
*
3)
0.65
Max.
100
Unit
mV
%/°C
Detecting voltage
Vs/ T
temperature coefficient
Low level output voltage
Output Leak current
Circuit current at ON time
Circuit current at OFF time
"H" transmission
delay time
"L" transmission
delay time
Threshold operating voltage
Output current
at ON time 1
Output current
at ON time 2
V
OL
I
OH
I
CCL
I
CCH
T
PLH
T
PHL
V
OPL
I
OL
1
I
OL
2
0.4
±0.1
9.0
5.0
V
µA
µA
µA
ms
µs
0.85
V
mA
mA
5
3
NOTE 1: T
PLH
: V
CC
=(V
S
typ. -0.4V) (V
S
typ. +0.4V)
NOTE 2 : T
PLH
: V
CC
=(V
S
typ. +0.4V) (V
S
typ. -0.4V)
NOTE 3 : Tables of PST92
series transmission delay time (Please see below.)
T
PLH
195
190
185
180
175
170
165
160
155
150
145
140
135
130
125
120
115
110
105
100
95
90
85
80
75
70
65
60
T
PHL
140
140
140
140
140
140
140
140
120
120
120
120
120
120
120
120
120
120
100
100
100
100
100
100
100
100
100
100
PST9246
PST9245
PST9244
PST9243
PST9242
PST9241
PST9240
PST9239
PST9238
PST9237
PST9236
PST9235
PST9234
PST9233
PST9232
PST9231
PST9230
PST9229
PST9228
PST9227
PST9226
PST9225
PST9224
PST9223
PST9222
PST9221
PST9220
PST9219
MITSUMI
System Reset PST92XX
Measuring Circuit
(1)
(2)
A : DC Amperemeter
V : DC Voltmeter
CRT : Oscilloscope
INPUT PULSE
Vs typ.+0.4V
Vs typ.-0.4V
0V
MITSUMI
System Reset PST92XX
Timing Chart
V
Vs
V
CC
Vs
>T
PLH
V
V
OUT
T
PLH
T
PLH
T
PLH
Application Circuit
If the impedance of V
CC
line is high enough, connect a
capacitor between V
CC
and GND terminal of the IC.
(NOTE 1)
NOTE 1 : When the rapid noise occurs to V
CC
, V
OUT
has sometimes switched over even if V
CC
doesn't become
below V
S
.
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