PI7VD9008HEVB datasheet, PDF - EEWORLD Datasheet

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PI7VD9008HEVB: DescriptionAdaptive EQ 4-channel 960H Video Decoder; File Size1MB，53 Pages; ManufacturerPericom Semiconductor Corporation (Diodes Incorporated); Websitehttps://www.diodes.com/

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PI7VD9008HEVB Overview

Adaptive EQ 4-channel 960H Video Decoder

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PI7VD9004ABH

Adaptive EQ 4-channel 960H Video Decoder

Features



Real time AEQ 4-channel Video/Audio decoder

for WD1(960H) and D1 cameras

Built-in Adaptive Equalizer(AEQ) for the best

picture image in the several hundred meter coax

cable condition

Proprietary Pericom AEQ technology recover

weak, noisy, or unstable analog input signals

Resilient SYNC TIP detection to lock video

signal in a noisy environment

Programmable sharpness, CTI, hue, saturation,

contrast and brightness

Support time multiplexed format of ITU-R

BT.656 output with 54/108MHz or72/144MHz

Provides a programmable mapping from four or

eight (non-real-time) analog video inputs to four

BT.656 digital outputs

NTSC(M), NTSC 4.43, PAL (B, D, G, H, I, M, Nc,

60) standard support

High performance 5H comb filter for all

NTSC/PAL standards

Built-in 10-bit audio Codec to allow 5analog

audio inputs and 1 audio output

Mixed audio analog output for multiple audio

channels

Two serial audio formats (I2S and DSP) are

supported for recording/mixing output and

playback input

Selectable Master and Slave serial audio interface

Multiple audio sample rates for 8, 16, 32, 44.1,

48KHz audio frequency



Integrated video PLL for 108MHz,144MHz clock

output

Two-wire serial interface(I

C) for register access

Provide system interrupt request for video

Packages: 128-pin LQFP



Description

PI7VD9004ABH is AEQ 4-Channel Video Decoders

and Audio Codec. Built-in Adaptive equalizer

(AEQ)recover the noisy signals caused by long or

small wire gauge Coax cables and display the best

picture image view quality. The video decoder

converts NTSC, PAL analog composite video

broadcasting signal (CVBS) into digital components

YCbCr for video controller or processor to perform

pre-view, compression and storage etc. The converted

digital video streams complying with ITU-R BT.656

are transported in time multiplexed format, which

contains one, two or four video channels.

Single 27MHz reference crystal clock support NTSC,

PAL and 960H standard resolution. Each video

channel contains 10-bit ADC, proprietary clamp,

automatic gain controller and 5H comb filter for

separating luminance & chrominance to reduce

artificial noise.



Application



Video Security DVRs, PC-DVR, Video Capture

cards

Automotive Camera Driver Assistant Systems

Video Broadcasting Equipment



Video/Audio signals

PI7VD9004ABH

4‐ch AEQ

Video Decoder

ITU‐R BT.656

H.264 Video

SoC

Cameras

Pericom Semiconductor Corporation

13-0174

www.pericom.com

PI7VD9004ABH

Adaptive EQ 4-channel 960H Video Decoder

Table of Contents

PI7VD9004ABH Block Diagram ............................................................................................................................................. 6

Pin Configuration(128-LQFP)................................................................................................................................................. 7

Pin-out Information .................................................................................................................................................................. 9

Functional Description ........................................................................................................................................................... 11

4.1

Video/Audio Analog Input .................................................................................................................................................... 11

4.2

Clamping and Automatic Gain Control............................................................................................................................... 11

4.3

Video Decoder ......................................................................................................................................................................... 11

4.4

Adaptive Equalization ............................................................................................................................................................. 11

4.5

Comb filter and Y/C Separation ............................................................................................................................................ 12

4.6

Video Signal Processing .......................................................................................................................................................... 12

4.7

Video Output Port ................................................................................................................................................................... 13

4.8

ANALOG AUDIO INPUT..................................................................................................................................................... 14

4.9

AUDIO PROCESSING ........................................................................................................................................................... 14

4.10

PI7VD9004ABH Cascade Mode ...................................................................................................................................... 17

4.11

C Host Interface ............................................................................................................................................................... 19

Configuration, Control, and Status Register Map .............................................................................................................. 20

Control Register ....................................................................................................................................................................... 21

6.1

REGISTERS .............................................................................................................................................................................. 21

6.1.1

VIDEO STATUS REGISTER – OFFSET 00H/10H/20H/30H (Default: 00H)..................................................... 21

6.1.2

BRIGHTNESS CONTROL REGISTER – OFFSET 01H/11H/21H/31H(Default=00H) .................................... 22

6.1.3

CONTRASTCONTROL REGISTER – OFFSET 02H/12H/22H/32H(Default=64H) ........................................ 22

6.1.4

SHARPNESS CONTROL REGISTER – OFFSET 03H/13H/23H/33H(Default=00H) ...................................... 22

6.1.5

CHROMA(U) GAIN REGISTER – OFFSET 04H/14H/24H/34H(Default=80H) .............................................. 22

6.1.6

CHROMA(V) GAIN REGISTER – OFFSET 05H/15H/25H/35H(Default=80H) .............................................. 23

6.1.7

HUECONTROL REGISTER – OFFSET 06H/16H/26H/36H(Default=00H) ...................................................... 23

6.1.8

RESERVED REGISTER– OFFSET07H/17H/27H/37H ......................................................................................... 23

6.1.9

RESERVED REGISTER – OFFSET 08H/18H/28H/38H ........................................................................................ 23

6.1.10

RESERVED REGISTER – OFFSET09H/19H/29H/39H ......................................................................................... 23

6.1.11

RESERVED REGISTER – OFFSET 0AH/1AH/2AH/3AH..................................................................................... 23

6.1.12

RESERVED REGISTER – OFFSET 0BH/1BH/2BH/3BH ...................................................................................... 23

6.1.13

RESERVED REGISTER – OFFSET 0CH/1CH/2CH/3CH ..................................................................................... 23

6.1.14

RESERVED REGISTER – OFFSET 0DH/1DH/2DH/3DH .................................................................................... 23

6.1.15

STANDARD SELECTION REGISTER – OFFSET 0EH/1EH/2EH/3EH(Default=77H) .................................. 23

6.1.16

RESERVEDREGISTER – OFFSET 0FH/1FH/2FH/3FH ........................................................................................ 23

6.1.17

RESERVED REGISTER – OFFSET 40H-50H .......................................................................................................... 23

6.1.18

FBITINV REGISTER – OFFSET 51H(Default=00H) ............................................................................................. 23

Pericom Semiconductor Corporation

13-0174

www.pericom.com

PI7VD9004ABH

Adaptive EQ 4-channel 960H Video Decoder

6.1.19

6.1.20

6.1.21

6.1.22

6.1.23

6.1.24

6.1.25

6.1.26

6.1.27

6.1.28

6.1.29

6.1.30

6.1.31

6.1.32

6.1.33

6.1.34

6.1.35

6.1.36

6.1.37

6.1.38

6.1.39

6.1.40

6.1.41

6.1.42

6.1.43

6.1.44

6.1.45

6.1.46

6.1.47

6.1.48

6.1.49

6.1.50

6.1.51

6.1.52

6.1.53

6.1.54

6.1.55

6.1.56

RESERVED REGISTER – OFFSET 52H-56H .......................................................................................................... 24

HBLEN REGISTER – OFFSET 57H/58H/59H/5AH(Default=90H) .................................................................... 24

RESERVED REGISTER – OFFSET 5BH ................................................................................................................... 24

BGCTL-REGISTER – OFFSET 5CH(Default=00H) ............................................................................................... 24

RESERVED REGISTER – OFFSET 5DH-5FH ......................................................................................................... 24

RESERVED REGISTER – OFFSET 60H ................................................................................................................... 24

CRYSTAL CLOCK SELECT REGISTER – OFFSET 61H(Default=03H) ............................................................ 24

36M/GPIO_OE REGISTER – OFFSET 62H(Default=00H)................................................................................... 24

CHANNEL ID01 REGISTER – OFFSET 63H(Default=10H) ................................................................................ 25

CHANNEL ID23 REGISTER – OFFSET 64H(Default=32H) ................................................................................ 25

PIXEL OUTPUT BUS TRI-STATE CONTROL REGISTER – OFFSET 65H(Default=00H) ........................... 25

RESERVED REGISTER – OFFSET 66-6FH ............................................................................................................. 26

AUDIO CLOCK CONTROL REGISTER – OFFSET 70H(Default=08H) ........................................................... 26

I2S AUDIO INPUT CONTROL REGISTER – OFFSET 71H(Default=00H) ...................................................... 26

RESERVED REGISTER – OFFSET72H-7AH .......................................................................................................... 26

SDOUT_M SELECT (R) REGISTER – OFFSET 7BH(Default=00H)................................................................... 26

SDOUT_M SELECT (L) REGISTER – OFFSET 7CH(Default=00H)................................................................... 27

EXTENDED LINE SELECT REGISTER – OFFSET 7DH(Default=E4H)............................................................ 27

SDOUT_M REGISTER– OFFSET 7EH(Default=00H) ......................................................................................... 28

MIX RATIO VALUE FOR LINE_IN4 REGISTER – OFFSET 7FH(Default=08H)............................................ 28

SOFTWARE RESET REGISTER– OFFSET 80H(Default=00H) ........................................................................... 29

RESERVED REGISTER – OFFSET 81H-84H .......................................................................................................... 29

VIDEO SOURCE SELECTION REGISTER – OFFSET 85H (Default=00H) ...................................................... 29

RESERVED REGISTER – OFFSET 86H-88H .......................................................................................................... 29

AUDIO FS MODE REGISTER– OFFSET 89H(Default=00H) .............................................................................. 29

RESERVED REGISTER – OFFSET 8AH-9EH ......................................................................................................... 30

PIXCLK 0 DELAY REGISTER– OFFSET 9FH(Default=00H) .............................................................................. 30

RESERVED REGISTER – OFFSET A0H-B0H ......................................................................................................... 30

CH8IDEN REGISTER – OFFSET B1H(Default=00H) ........................................................................................... 30

RESERVED REGISTER – OFFSET B2H-C7H ......................................................................................................... 30

GPIO_0_1 MODE REGISTER– OFFSET C8H(Default=00H) .............................................................................. 30

GPIO_2_3 MODE REGISTER– OFFSET C9H(Default=00H) .............................................................................. 31

VIDEO OUTPUT MODE REGISTER – OFFSET CAH(Default=00H)............................................................... 31

GPIO POLARITY REGISTER – OFFSET CBH (Default=00H) ............................................................................ 32

PIXOUT OUTPUT CH2 SELECT REGISTER – OFFSET CCH (Default=39H) ................................................ 32

PIXOUT OUTPUT CH1 SELECT REGISTER – OFFSET CDH (Default=E4H) ............................................... 32

RESERVED REGISTER– OFFSET CEH ................................................................................................................... 33

SERIAL MODE CONTROL REGISTER– OFFSET CFH(Default=00H) ............................................................. 33

Pericom Semiconductor Corporation

13-0174

www.pericom.com

PI7VD9004ABH

Adaptive EQ 4-channel 960H Video Decoder

6.1.57

6.1.58

6.1.59

6.1.60

6.1.61

6.1.62

6.1.63

6.1.64

6.1.65

6.1.66

6.1.67

6.1.68

6.1.69

6.1.70

6.1.71

6.1.72

6.1.73

6.1.74

6.1.75

6.1.76

6.1.77

6.1.78

6.1.79

6.1.80

7.1

7.2

7.3

RESERVED REGISTER– OFFSET D0H-D1H ......................................................................................................... 33

SDOUT_RM OUTPUT REGISTER– OFFSET D2H(Default=03H) .................................................................... 33

SDOUT_R_SEQ_1_0 REGISTER– OFFSET D3H(Default=10H) ........................................................................ 34

SDOUT_R_SEQ_3_2 REGISTER– OFFSET D4H(Default=32H) ........................................................................ 34

SDOUT_R_SEQ_5_4 REGISTER– OFFSET D5H(Default=54H) ........................................................................ 35

SDOUT_R_SEQ_7_6REGISTER– OFFSETD6H(Default=76H) .......................................................................... 36

SDOUT_R_SEQ_9_8 REGISTER– OFFSET D7H(Default=98H) ........................................................................ 37

SDOUT_R_SEQ_B_A REGISTER– OFFSET D8H(Default= BAH) .................................................................... 37

SDOUT_R_SEQ_D_C REGISTER– OFFSET D9H(Default= DCH) ................................................................... 38

SDOUT_R_SEQ_F_E REGISTER– OFFSET DAH(Default= FEH) ..................................................................... 39

I2S MASTER CONTROL REGISTER– OFFSET DBH(Default= C2H) ............................................................... 40

MIX_MUTE REGISTER– OFFSET DCH(Default=00H) ...................................................................................... 40

MIX RATIO VALUE FOR LINE_IN0 & LINE_IN1 REGISTER – OFFSET DDH (Default=88H) ................. 40

MIX RATIO VALUE FOR LINE_IN2 & LINE_IN3 REGISTER – OFFSET DEH (Default=88H).................. 41

PB RATIO REGISTER – OFFSET DFH (Default=08H) ......................................................................................... 41

MIXING OUTPUT CONTROL REGISTER– OFFSET E0H(Default=14H) ....................................................... 42

RESERVED REGISTER– OFFSET E1H-F8H........................................................................................................... 42

PIXCLK OUTPUT MODE REGISTER– OFFSET F9H (Default=00H)............................................................... 42

CCIR656 CONTROL REGISTER– OFFSET FAH(Default=00H) ........................................................................ 43

CLOCK POLARITY REGISTER– OFFSET FBH(Default=0FH) .......................................................................... 43

VIDEO/AUDIO DETECTION ENABLE REGISTER–OFFSET FCH (Default=FFH) ...................................... 44

VIDEO/AUDIO DETECTION STATUS REGISTER–OFFSET FDH (Default=00H) ...................................... 44

DEVICE ID_H REGISTER– OFFSET FEH(Default=00H) .................................................................................... 44

DEVICE ID - L REGISTER– OFFSET FFH(Default=E8H) ................................................................................... 45

Electrical Characteristics......................................................................................................................................................... 45

Absolute Maximum Ratings................................................................................................................................................... 45

Operating Conditions ............................................................................................................................................................. 45

DC Electrical Characteristics ................................................................................................................................................. 45

Power Dissipation ......................................................................................................................................................... 46

Power-On Sequence of 3.3V and 1.0V Power ........................................................................................................... 46

Crystal Specifications .................................................................................................................................................... 46

Audio Electrical Characteristics .................................................................................................................................. 47

Pixel Clock and Video Data Timing ........................................................................................................................... 47

Audio Interface Timing ................................................................................................................................................ 49

I2C Host Port Timing ................................................................................................................................................... 50

7.3.1

7.3.2

7.3.3

7.4

7.4.1

7.4.2

7.4.3

7.4.5

AC Electrical Characteristics.................................................................................................................................................. 46

Packaging Mechanical ............................................................................................................................................................. 51

Ordering Information ............................................................................................................................................................. 52

Pericom Semiconductor Corporation

13-0174

www.pericom.com

PI7VD9008HEVB Related Products

	PI7VD9008HEVB	PI7C9X9204S	PI7C9X9208	PI7VD9208HEVB	PI7VD9004ABHFD	PI7VD9008H	PI7VD9004H
Description	Adaptive EQ 4-channel 960H Video Decoder	Adaptive EQ 4-channel 960H Video Decoder	Adaptive EQ 4-channel 960H Video Decoder	Adaptive EQ 4-channel 960H Video Decoder	Adaptive EQ 4-channel 960H Video Decoder	Adaptive EQ 4-channel 960H Video Decoder	Adaptive EQ 4-channel 960H Video Decoder

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