Multimedia ICs
SYNC separator IC with AFC
BA7046 / BA7046F
The BA7046 and BA7046F separate the synchronization signals from a video signal and output the horizontal and
vertical synchronization signals (H
D
and V
D
), and the composite synchronization signal (Sync-out).
The H
D
and V
D
pulse phase difference is guaranteed.
•
Applications
TVs and VCRs
•
FeaturesAFC circuit.
1) Built-in
2) H
D
and V
D
phase difference guaranteed.
3) Low power dissipation. (approx. 21mW)
4) Low external parts count.
5) 8-pin DIP / SOP package.
6) Horizontal free-run frequency does not require
adjustment.
•
Absolute maximum ratings (Ta = 25°C)
BA7046 (DIP)
Parameter
Power supply voltage
Power dissipation
Operating temperature
Storage temperature
Symbol
V
CC Max.
Pd
Topr
Tstg
Limits
8.0
500
∗
– 20 ~ + 75
– 55 ~ + 125
Unit
V
mV
°C
°C
∗
Reduced by 5mW for each increase in Ta of 1°C over 25°C.
BA7046F (SOP)
Parameter
Power supply voltage
Power dissipation
Operating temperature
Storage temperature
over 25°C.
Symbol
V
CC Max.
Pd
Topr
Tstg
Limits
8.0
350
∗
– 20 ~ + 75
– 55 ~ + 125
Unit
V
mW
°C
°C
∗
When mounted on a 50mm
×
50mm PCB board, reduced by 3.5mW for each increase in Ta of 1°C
•
Recommended operating conditions (Ta = 25°C)
Parameter
Operating power supply voltage
Symbol
V
CC
Min.
4.5
Typ.
—
Max.
5.5
Unit
V
1
Multimedia ICs
BA7046 / BA7046F
•
Block diagrams
1
H. OSC
PHASE
COMP
8
2
7
3
SYNC
SEPA
6
4
V. SEPA
5
•
Pin descriptions
Pin No.
1
2
3
4
5
6
7
8
Function
Horizontal oscillator resistor
H
D
output
SYNC output (open collector)
V
D
output
GND
Video input
Power supply
Phase comparator output
•
Input / output circuits
V
CC
V
CC
12k
200
1k
1pin
100µA
5k
2pin
200
3pin
Fig. 1
Fig. 2
V
CC
Fig. 3
V
CC
3k 3k 3k
V
CC
10k
200
1k
4pin
100
10µA
3k 3k 3k
6pin
8pin
Fig. 4
Fig. 5
Fig. 6
2
Multimedia ICs
BA7046 / BA7046F
CC
•
Electrical characteristics (unless otherwise noted Ta = 25°C and V
Parameter
Quiescent current
Minimum synchronization separation level
Pulse voltage, LOW
Pulse voltage, HIGH
(Horizontal) free-running frequency
Capture range
Lock-in phase difference
H
D
, V
D
phase difference
H
D
pulse width
V
D
pulse width
Not designed for radiation resistance.
= 5.0V)
Conditions
pin 3 open
pin 6 terminated with 75Ω resistor
pins 2, 4
pins 2, 4
No input signal, I
1
= open
Symbol Min.
I
Q
V
syn-Min.
V
P-L
V
P-H
f
H-O
2.0
—
—
4.7
13.9
Typ.
4.1
0.08
0.1
4.9
15.7
±
2.9
0
23.5
5.1
230
Max.
6.2
0.15
0.3
—
17.5
—
+ 1.0
30.0
5.6
270
Unit
mA
V
P-P
V
V
kHz
kHz
µs
µs
µs
µs
pin2
pin4
pin2
pin4
pin– 6
pin– 2
∆f
CAP
±
2.1
T
HPH
– 1.0
T
HVD
T
HD
T
VD
17.0
4.6
190
•
Measurement circuit
1µ
2200p
0.022µ
47µ
Video In
+
39k
V
CC
8
A
7
+
75
1µ
6
+
5
470k
1
2
3
4
I
I
100p
130k
V
T
10k
V
V
CC
T
V
T
Fig. 7
•
Circuit operation separation circuit
(1) Synchronization
Detects the charging current to a externally-connected
capacitor, and performs synchronization separation.
(2) Horizontal oscillation circuit
When a video signal is input, it is synchronized with
Hsync by the PLL. The horizontal free-running frequency
is determined by external resistor R1.
2.05E6
[kHz]
f
H-O
=
R
1
(3) Vertical synchronization separation circuit
When a video signal is input, synchronization signal
separation is done over the vertical synchronization
pulse interval.
3
Multimedia ICs
BA7046 / BA7046F
•
V , H
IN
D
and V
D
timing charts
Vertical synchronization pulse interval
NTSC signal
Odd field (IN)
1 / 2H
NTSC signal
Even field (IN)
V
D
(OUT)
H
D
, V
D
phase difference
H
D
Odd field (OUT)
H
D
Even field (OUT)
Fig. 8
(1) The rise and fall positions for V
D
are basically the same for both odd and even fields.
(2) H
D
shifts by 1 / 2H during the odd and even field interval.
(3) Only the odd field is given for the specification.
4
Multimedia ICs
BA7046 / BA7046F
•
Application example
R
2
470k
C
4
100p
R
1
130k
V
CC
= 5V
PHASE
COMP
1
H. OSC
8
∗
R
3
10k
C
2
2200p
V
CC
= 5V
+
C
3
1µ
+
C
5
47µ
C
6
0.022µ
10k
H
D
2
7
C
1
SYNC
SEPA
V. SEPA
R
4
330
C
7
Vsig
SYNC
3
6
R
5
+
470k
1µ
1000p
V
D
4
5
∗
By configuring the circuit enclosed in the dotted line to that in the
diagram on the right, you can decrease the lock-in time and increase the
capture range.
V
CC
R
2
470k
R
3
10k
8
C
2
2200p
C
3-1
0.47µ
C
3-2
0.47µ
Fig.9
• When SYNC SEPA output only is used. H
D
and V
D
unused.
V
CC
= 5V
R
1
120k
1
H. OSC
PHASE
COMP
8
V
CC
= 5V
+
C
5
47µ
C
6
0.022µ
10k
H
D
2
7
C
1
SYNC
SEPA
V. SEPA
R
4
330
C
7
Vsig
SYNC
3
6
R
5
+
470k
1µ
1000p
V
D
4
5
Fig. 10
(1) Connect pin 1 to GND via a 120kΩ (approx.) resistor. Leave pins 2, 4 and 8 open.
(2) SYNC output polarity (pin 3) is positive.
(3) The delay time for rising edge of the SYNC output (pin 3) with respect to the falling edge of Sync for the Vsig
input signal (pin 6) is 850ns (reference value).
(4) The delay time for falling edge of the SYNC output (pin 3) with respect to the rising edge of Sync for the Vsig
input signal (pin 6) is 450ns (reference value).
•
Attached components a tolerance of ± 2%, and a temperature coefficient of 100ppm or lower.
Resistor R should have
1
5
京公网安备 11010802033920号
EEWORLD
