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BUK555-100

Description
PowerMOS transistor Logic level FET
Categorysemiconductor    Discrete semiconductor   
File Size51KB,7 Pages
ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.)
Websitehttps://www.nxp.com/
Download Datasheet View All

BUK555-100 Overview

PowerMOS transistor Logic level FET

Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
BUK555-100A/B
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
BUK555
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
V
GS
= 5 V
MAX.
-100A
100
25
125
175
0.085
MAX.
-100B
100
22
125
175
0.11
UNIT
V
A
W
˚C
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
1 23
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
±V
GSM
I
D
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
t
p
50
µs
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
-
MIN.
-
-
-
-
-
-
-
-
- 55
-
-100A
25
18
100
125
175
175
MAX.
100
100
15
20
-100B
22
15
88
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
-
TYP.
-
60
MAX.
1.2
-
UNIT
K/W
K/W
April 1993
1
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