Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
DATA SHEET
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
•
•
•
•
Four low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See
Section, “Applications Information”,
section,
“Wiring
the Differential Input to Accept Single-Ended Levels”
(Figures 1A
and 1B)
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input, (input select)
Output skew: 5ps (typical), at 3.63V
Propagation delay: 200ps (typical), at 3.63V
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
Maximum device current consumption (I
EE
): 60mA (maximum),
at 3.63V
Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
Lead-free (RoHS 6), 16-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature
105°C operations
•
•
•
•
•
•
•
•
•
•
Block Diagram
V
CC
Pin Assignment
nQ3
nQ2
Q3
Q2
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
V
EE
1
SEL
2
16 15 14 13
12 nQ1
11 Q1
10 nQ0
9 Q0
5
V
CC
PCLK1 3
nPCLK1 4
6
PCLK0
0
1
f
REF
7
nPCLK0
8
V
REF
V
CC
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
SEL
V
REF
Pulldown
Voltage
Reference
8SLVP1204 REVISION D 6/8/15
1
©2015 Integrated Device Technology, Inc.
8SLVP1204 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 10
11, 12
13, 14
15, 16
Name
V
EE
SEL
PCLK1
nPCLK1
V
CC
PCLK0
nPCLK0
V
REF
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Power
Input
Input
Input
Power
Input
Input
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Negative supply pin.
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface
levels.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left floating.
Power supply pins.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left floating.
Bias voltage reference for the PCLK inputs.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table
Input
SEL
0 (default)
1
Operation
PCLK0, nPCLK0 is the selected differential clock input.
PCLK1, nPCLK1 is the selected differential clock input.
NOTE: SEL is an asynchronous control.
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REVISION D 6/8/15
8SLVP1204 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q3 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
2.97
Typical
3.3V
53
170
Maximum
3.63
60
204
Units
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= 3.3V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q3 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
53
170
Maximum
3.465
60
204
Units
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
CC
= 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 to Q3 terminated 50 to V
CC
– 2V
Test Conditions
Minimum
2.375
Typical
2.5V
49
170
Maximum
2.625
55
199
Units
V
mA
mA
REVISION D 6/8/15
3
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP1204 DATA SHEET
Table 4D. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.63V
V
CC
= 2.625V
Input Low Voltage
Input High Current
Input Low Current
SEL
SEL
V
CC
= 3.63V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 4E. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ±5% or 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
Input High Current
Input Low Current
SEL
SEL
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REVISION D 6/8/15
8SLVP1204 DATA SHEET
Table 4F. LVPECL DC Characteristics,
V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Reference Voltage for Input Bias
Output High Voltage
1
Output Low Voltage
1
Test Conditions
V
CC
= V
IN
= 3.63V
V
CC
= 3.63V, V
IN
= 0V
V
CC
= 3.63V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.65
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
Table 4G. LVPECL DC Characteristics,
V
CC
= 3.3V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Reference Voltage for Input Bias
Output High Voltage
1
Output Low Voltage
1
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.65
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
Table 4H. LVPECL DC Characteristics,
V
CC
= 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Reference Voltage for Input Bias
Output High Voltage
1
Output Low Voltage
1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE 1. Outputs terminated with 50 to V
CC
– 2V.
REVISION D 6/8/15
5
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
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