W3H128M72E-400SBM datasheet, PDF

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W3H128M72E-400SBM: DescriptionDDR DRAM, 128MX72, 1.35ns, CMOS, PBGA208, BGA-208; Categorystorage storage; File Size1MB，31 Pages; ManufacturerMercury Systems Inc

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W3H128M72E-400SBM Overview

DDR DRAM, 128MX72, 1.35ns, CMOS, PBGA208, BGA-208

W3H128M72E-400SBM Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Mercury Systems Inc
package instruction	BGA-208
Reach Compliance Code	unknow
access mode	MULTI BANK PAGE BURST
Maximum access time	1.35 ns
Other features	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH; LG-MAX; WD-MAX; SEATED HGT-CALCULATED
JESD-30 code	R-PBGA-B208
length	22.1 mm
memory density	9663676416 bi
Memory IC Type	DDR DRAM
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	208
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128MX72
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Maximum seat height	5.07 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	16.1 mm

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1GB – 128M x 72 DDR2 SDRAM

208 PBGA Multi-Chip Package

W3H128M72E-XSBX / W3H128M72E-XNBX

FEATURES



Data rate = 667, 533, 400



Package:

• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm

• 1.0mm pitch



Core Supply Voltage = 1.8V



I/O Supply Voltage = 1.8V - (SSTL_18 compatible)



Differential data strobe (DQS, DQS#) per byte



Internal, pipelined, double data rate architecture



4-bit prefetch architecture



DLL for alignment of DQ and DQS transitions with clock

signal



Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)



Programmable Burst lengths: 4 or 8



Auto Refresh and Self Refresh Modes



On Die Termination (ODT)



Adjustable data – output drive strength



Programmable CAS latency (CL)



Posted CAS additive latency (AL)



CK/CK# Termination options available

• 0 ohm, 20 ohm



Write latency = Read latency - 1* t



Commercial, Industrial and Military Temperature Ranges



Organized as 128M x 72



Weight: W3H128M72E-XSBX - 4 grams max



Weight: W3H128M72E-XNBX - TBD

BENEFITS



56% space savings vs. FBGA



Reduced part count



50% I/O reduction vs FBGA



Reduced trace lengths for lower parasitic capacitance



Suitable for hi-reliability applications

* This product is subject to change without notice.

TYPICAL APPLICATION

RAM

Host

FPGA/

Processor

DDR2 / DDR3

W3H128M72E-XSBX / -XNBX

SSD (SLC)

MSM032 / MSM064 (SATA BGA)

W7N16GVHxxBI (PATA BGA)

5in

)

MSD1TB / 512 / 256 / 128 (SATA, 2.5in)

FIGURE 1 – DENSITY COMPARISONS

CSP Approach (mm)

11.5

14.0

FBGA

W3H128M72E-XXXX

56%

50%

Area

I/O Count

5 x 161mm

= 805mm

5 x 84 balls = 420 balls

352mm

208 Balls

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com

4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

W3H128M72E-XSBX / W3H128M72E-XNBX

TABLE 1 – BALL DESCRIPTIONS

Symbol

ODT

CK, CK#

Type

Input

Description

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only

applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if

disabled via the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge

of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The

speciﬁc circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conﬁguration and operating mode. CKE LOW provides

PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE

is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during

self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V

is applied during

ﬁ

rst power-up. After V

REF

has

become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For

proper SELF-REFRESH operation, V

REF

must be maintained.

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when

CS# is registered HIGH.

Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁne the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a

WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of

DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4

Bank address inputs: BA0–BA2 deﬁne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–

BA2 deﬁne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10

HIGH) The address inputs also provide the op-code during a LOAD MODE command.

Data input/output: Bidirectional data bus

Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read

data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read

data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

Power Supply: I/O + core, V

CCQ

is common to V

SSTL_18 reference voltage.

Ground

No connect: These balls should be left unconnected.

Future use; address bits A14 and A15 are reserved for future densities.

CKE

Input

CS#

RAS#, CAS#, WE#

LDM, UDM

BA0–BA2

Input

A0-A13

Input

DQ0-71

UDQS, UDQS#

I/O

LDQS, LDQS#

REF

DNU

I/O

Supply

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com

4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

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