Field Programmable Gate Array, 50MHz, 64-Cell, CMOS, PDIP48,
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Monolithic Memories |
| Reach Compliance Code | unknow |
| maximum clock frequency | 50 MHz |
| JESD-30 code | R-PDIP-T48 |
| JESD-609 code | e0 |
| Number of entries | 40 |
| Number of logical units | 64 |
| Output times | 40 |
| Number of terminals | 48 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Package body material | PLASTIC |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP48,.6 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| surface mount | NO |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
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