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K9F5608U0: Description32M x 8 Bit NAND Flash Memory; File Size436KB，29 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K9F5608U0 Overview

32M x 8 Bit NAND Flash Memory

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K9F5608U0A-YCB0,K9F5608U0A-YIB0

Document Title

32M x 8 Bit NAND Flash Memory

FLASH MEMORY

Revision History

Revision No. History

0.0

Initial issue.

Draft Date

July 17th 2000

Remark

Advanced

Information

Preliminary

0.1

1. Support copy-back program

- The copy-back program is configured to quickly and efficiently rewrite

data stored in one page within the array to another page within the

same array without utilizing an external memory. Since the time-con

suming sequently-reading and its re-loading cycles are removed, the

system performance is improved. The benefit is especially obvious

when a portion of a block is updated so that the rest of the block also

need to be copied to the newly assigned free block.

Oct. 4th 2000

0.2

Nov. 20th 2000

1. Explain how pointer operation works in detail.

2. For partial page programming into the copied page

- Once the copy-back Program is finished, any additional partial page

programming into the copied pages is prohibited before erase.

3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)

- The SE input controls the access of the spare area. When SE is high,

the spare area is not accessible for reading or programming. SE is rec

ommended to be coupled to GND or Vcc and should not be toggled

during reading or programming.

=> Connect this input pin to GND or set to static low state unless the

sequential read mode excluding spare area is used.

4. Updated operation for tRST timing

- If reset command(FFh) is written at Ready state, the device goes into

Busy for maximum 5us.

1. In addition, explain WE function in pin description

- The WE must be held high when outputs are activated.

1.Powerup sequence is added

: Recovery time of minimum 1µs is required before internal circuit gets

ready for any command sequences

~ 2.5V

Preliminary

0.3

Mar. 2th 2001

0.4

Jul. 22th 2001

≈

~ 2.5V

High

2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.

3. AC parameter tAR1 value : 100ns --> 20ns

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.

http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have

any questions, please contact the SAMSUNG branch office near you.

≈

1µ

≈

K9F5608U0A-YCB0,K9F5608U0A-YIB0

PRODUCT INTRODUCTION

FLASH MEMORY

The K9F5608U0A is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare sixteen columns

are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data

transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16

cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32

pages formed by two NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. The

program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory

array consists of 2048 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the

K9F5608U0A.

The K9F5608U0A has addresses multiplexed into 8 I/O′s. This scheme dramatically reduces pin counts and allows systems upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O′s by

bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except

for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address

loading. The 32M byte physical space requires 25 addresses, thereby requiring three cycles for byte-level addressing: column

address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles fol-

lowing the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations

are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F5608U0A.

Table 1. COMMAND SETS

Function

Read ID

Reset

Page Program

Copy-Back Program

Block Erase

Read Status

1st. Cycle

00h/01h

(1)

50h

(2)

90h

FFh

80h

00h

60h

70h

2nd. Cycle

10h

8Ah

D0h

Acceptable Command during Busy

NOTE

: 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is

automatically moved to the 1st half register(00h) on the next cycle.

2. The 50h command is valid only when the GND input(pin # 6) is low level.

Caution

: Any undefined command inputs are prohibited except for above command set of Table 1.

K9F5608U0A-YCB0,K9F5608U0A-YIB0

PIN DESCRIPTION

Command Latch Enable(CLE)

FLASH MEMORY

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched

into the command register through the I/O ports on the rising edge of the WE signal.

Address Latch Enable(ALE)

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of

WE with ALE high.

Chip Enable(CE)

The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.

However, when the device is in the Busy state during program or erase, CE high is ignored, and does not return the device to

standby mode.

Write Enable(WE)

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

The WE must be held high when outputs are activated.

Read Enable(RE)

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge

of RE which also increments the internal column address counter by one.

GND (Pin # 6)

Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.

I/O Port : I/O 0 ~ I/O 7

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z

when the chip is deselected or when the outputs are disabled.

Write Protect(WP)

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when

the WP pin is active low.

Ready/Busy(R/B)

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is

in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip

is deselected or when outputs are disabled.

K9F5608U0 Related Products

	K9F5608U0	K9F5608U0A-YIB0	K9F5608U0A-YCB0	K9F5608U0A
Description	32M x 8 Bit NAND Flash Memory	32M x 8 Bit NAND Flash Memory	32M x 8 Bit NAND Flash Memory	32M x 8 Bit NAND Flash Memory

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