TC58NS256DC
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
256-MBIT (32M
×
8 BITS) CMOS NAND E PROM (32M BYTE SmartMedia
DESCRIPTION
2
TM
)
The TC58NS256 is a single 3.3-V 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as 528 bytes
×
32 pages
×
2048 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell
array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes
+
512 bytes:
528 bytes
×
32 pages).
The TC58NS256 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed.
The TC58NS256DC is a SmartMedia
TM
with ID and each device has 128 bit unique ID number embedded in the
device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright
protection is required.
The data stored in the TC58NS256DC needs to comply with the data format standardized by the SSFDC Forum
in order to maintain compatibility with other SmartMedia
TM
systems.
FEATURES
•
Organization
Memory cell array
528
×
64K
×
8
Register
528
×
8
Page size
528 bytes
Block size
(16K
+
512) bytes
Modes
Read, Reset, Auto Page Program,
Auto Block Erase, Status Read
Mode control
Serial input/output, Command control
Complies with the SmartMedia
TM
Electrical
Specification and Data Format Specification
issued by the SSFDC Forum
•
•
•
Power supply
V
CC
=
3.3 V
±
0.3 V
Access time
Cell array-register
25
µs
max
Serial Read cycle
50 ns min
Operating current
Read (50-ns cycle)
10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
100
µA
max
Package
TC58NS256DC: FDC-22A (Weight: 1.8 g typ.)
•
•
•
•
PIN ASSIGNMENT
(TOP VIEW)
V
SS
CLE ALE
PIN NAMES
I/O4 V
SS
V
SS
WE
WP
I/O1 I/O2
I/O3
I/O1~I/O8
CE
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground Input
Low Voltage Detect
Power supply
Ground
TM
WE
RE
CLE
ALE
WP
1
2
3
4
5
6
7
8
9 10 11
RY/BY
GND
LVD
22 21 20 19 18 17 16 15 14 13 12
V
CC
V
SS
V
CC
CE
RE
RY/BY
GND LVD I/O8 I/O7 I/O6 I/O5 V
CC
is a trademark of Toshiba Corporation.
000707EBA2
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
2000-08-27
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TC58NS256DC
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
0°~55°C, V
CC
=
3.3 V
±
0.3 V)
SYMBOL
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
WC
t
WH
t
WW
t
RR
t
RP
t
RC
t
REA
t
CEH
t
REAID
t
OH
t
RHZ
t
CHZ
t
REH
t
IR
t
RSTO
t
CSTO
t
RHW
t
WHC
t
WHR
t
AR1
t
CR
t
R
t
WB
t
AR2
t
RB
t
CRY
t
RST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
PARAMETER
MIN
0
10
0
10
25
0
10
20
10
50
15
100
20
35
50
100
10
15
0
0
30
30
100
100
50
MAX
35
35
30
20
35
45
25
200
200
600
+
t
r
(
RY/BY
)
6/10/500
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
(1)
(2)
NOTES
WE
-High Hold Time
WP
High to
WE
Low
Ready-to-
RE
Falling Edge
Read Pulse Width
Read Cycle Time
RE
Access Time (Serial Data Access)
CE -High Time for Last Address in Serial Read Cycle
RE
Access Time (ID Read)
Data Output Hold Time
RE
-High-to-Output-High Impedance
CE -High-to-Output-High Impedance
RE
-High Hold Time
Output-High-Impedance-to-
RE
Rising Edge
RE
Access Time (Status Read)
CE Access Time (Status Read)
RE
High to
WE
Low
WE
High to CE Low
WE
High to
RE
Low
ALE Low to
RE
Low (ID Read)
CE Low to
RE
Low (ID Read)
Memory Cell Array to Starting Address
WE
High to Busy
ALE Low to
RE
Low (Read Cycle)
RE
Last Clock Rising Edge to Busy (in Sequential Read)
CE High to Ready (When interrupted by CE in Read Mode)
Device Reset Time (Read/Program/Erase)
AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
VALUES
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
C
L
(100 pF)
+
1 TTL
2000-08-27
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TC58NS256DC
Notes:
(1)
CE High to Ready time depends on the pull-up resistor tied to the RY/ BY pin.
(Refer to Application Note (7) toward the end of this document.)
(2)
Sequential Read is terminated when t
CEH
is greater than or equal to 100 ns.
If the RE to CE delay is less than 30 ns, RY/ BY signal stays Ready.
t
CEH
≥
100 ns
*
CE
*:
V
IH
or V
IL
RE
525
526
527
A
A : 0~30 ns
→
Busy signal is not output.
RY/BY
Busy
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta
=
0°~55°C, V
CC
=
3.3 V
±
0.3 V)
SYMBOL
t
PROG
N
t
BERASE
P/E
PARAMETER
Programming Time
Number of Programming Cycles on Same
Page
Block Erasing Time
Number of Program/Erase Cycles
MIN
TYP.
200
3
MAX
1000
10
4
2.5 x 10
5
ms
(2)
UNIT
µs
(1)
NOTES
(1) Refer to Application Note 12 toward the end of this document.
(2) Refer to Application Note 15 toward the end of this document.
2000-08-27
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