PBM 3960/1
Sign
2
V
ref
DA
1
Sign
1
CD
1
V
DD
WR
D7
D6
D5
D4
D3
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
Reset
DA
2
Sign
2
CD
2
V
SS
CS
A1
A0
D0
D1
D2
N/C
DA
2
Reset
5
6
7
8
9
10
11
CD
2
V
SS
CS
28
27
26
4
3
2
1
N/C
A1
A0
25
24
D0
D1
D2
N/C
D3
D4
D5
PBM
3960/1N
18
17
16
15
14
13
12
N/C
V
ref
DA
1
N/C
PBM
3960/1QN
23
22
21
20
19
12
13
14
15
16
17
Sign
1
CD
1
V
DD
Figure 4. Pin configuration.
Pin Descriptions
Refer to figure 4.
DIP
PLCC
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
12
13
14
15
16
17
19
20
21
23
24
25
27
28
1
2
3
4
6
7
5
8
11
18
22
26
V
Ref
DA
1
Sign
1
CD
1
V
DD
WR
D7
D6
D5
D4
D3
D2
D1
D0
A0
A1
CS
V
SS
CD
2
Sign
2
DA
2
Reset
Voltage reference supply pin, 2.5 V nominal (3.0 V maximum)
Digital-to-Analog 1, voltage output. Output between 0.0 V and V
R
- 1 LSB.
Sign 1, TTL/CMOS level. To be connected directly to PBL 3771 Phase input.
Databit D7 is transfered non inverted from PBM 3960/1/1 data input.
Current Decay 1, TTL/CMOS level. The signal is automatically generated when
decay level is programmed. LOW level = fast current decay.
Voltage Drain-Drain, logic supply voltage. Normally +5 V.
Write, TTL/CMOS level, input for writing to internal registers.
Data is clocked into flip flops on positive edge.
Data 7, TTL/CMOS level, input to set data bit 7 in data word.
Data 6, TTL/CMOS level, input to set data bit 6 in data word.
Data 5, TTL/CMOS level, input to set data bit 5 in data word.
Data 4, TTL/CMOS level, input to set data bit 4 in data word.
Data 3, TTL/CMOS level, input to set data bit 3 in data word.
Data 2, TTL/CMOS level, input to set data bit 2 in data word.
Data 1, TTL/CMOS level, input to set data bit 1 in data word.
Data 0, TTL/CMOS level, input to set data bit 0 in data word.
Address 0, TTL/CMOS level, input to select data transfer,
A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH).
Address 1, TTL/CMOS level, input to select data transfer. A1 selects between normal
D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH).
Chip Select, TTL/CMOS level, input to select chip and activate data transfer
from data inputs. LOW level = chip is selected.
Voltage Source-Source. Ground pin, 0 V reference for all signals and
measurements unless otherwise noted.
Current Decay 2, TTL/CMOS level. The signal is automatically generated
when decay level is programmed. LOW level = fast current decay .
Sign 2. TTL/CMOS level. To be connected directly to PBL 3771 sign input.
Data bit D7 is transfered non-inverted from PBM 3960/1 data input.
Digital-to-Analog 2, voltage output. Output between 0.0 V and V
ref
- 1 LSB.
Reset, digital input resetting internal registers.
HIGH level = Reset, V
Res
≥
3.5 V = HIGH level. Pulled low internally.
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
Not Connected
4
WR
N/C
D7
D6
18
PBM 3960/1
Definition of Terms
Resolution
Resolution is defined as the reciprocal of
the number of discrete steps in the DAC
output. It is directly related to the
number of switches or bits within the
DAC. For example, PBM 3960/1 has 2
7
,
or 128, output levels and therefor has 7
bits resolution. Remember that this is
not equal to the number of microsteps
available.
Linearity Error
Linearity error is the maximum deviation
from a straight line passing through the
end points of the DAC transfer
characteristic. It is measured after
adjusting for zero and full scale.
Linearity error is a parameter intrinsic to
the device and cannot be externally
adjusted.
Power Supply Sensitivity
Power supply sensitivity is a measure of
the effect of power supply changes on
the DAC full-scale output.
Settling Time
Full-scale current settling time requires
zero-to-full-scale or full-scale-to-zero
output change. Settling time is the time
required from a code transition until the
DAC output reaches within
±
1
/
2
LSB of
the final output value.
Full-scale Error
Full-scale error is a measure of the
output error between an ideal DAC and
the actual device output.
Differential Non-linearity
The difference between any two
consecutive codes in the transfer curve
from the theoretical 1LSB, is differential
non-linearity
Monotonic
If the output of a DAC increases for
increasing digital input code, then the
DAC is monotonic. A 7-bit DAC which is
monotonic to 7 bits simply means that
increasing digital input codes will
produce an increasing analog output.
PBM 3960/1 is monotonic to 7 bits.
different levels for initiation of fast
current decay can be selected.
The sign outputs generate the phase
shifts, i.e., they reverse the current
direction in the phase windings.
Data Bus Interface
PBM 3960/1 is designed to be compat-
ible with 8-bit microprocessors such as
the 6800, 6801, 6803, 6808, 6809, 8051,
8085, Z80 and other popular types and
their 16/32 bit counter parts in 8 bit data
mode. The data bus interface consists of
8 data bits, write signal, chip select, and
two address pins. All inputs are TTL-
compatible (except reset). The two
address pins control data transfer to the
four internal D-type registers. Data is
transferred according to figure 10 and on
the positive edge of the write signal.
Current Direction, Sign
1
& Sign
2
These bits are transferred from D
7
when
writing in the respective DA register. A
0
and A
1
must be set according to the data
transfer table in figure 10.
Current Decay, CD
1
& CD
2
CD
1
and CD
2
are two active low signals
(LOW = fast current decay). CD
1
is
active if the previous value of DA-Data1
is strictly larger than the new value of
DA-Data1 and the value of the level
register LEVEL1 (L
61
… L
41
) is strictly
larger than the new value of DA-Data1.
CD
1
is updated every time a new value
is loaded into DA-Data1. The logic
definition of CD
1
is:
CD
1
= NOT{[(D
6
… D
0
) < (Q
61
… Q
01
)]
AND[(D
6
…D
4
) < (L
61
… L
41
)]}
Functional Description
Each DAC channel contains two
registers, a digital comparator, a flip flop,
and a D/A converter. A block diagram is
shown on the first page. One of the
registers stores the current level, below
which, fast current decay is initiated.
The status of the CD outputs determines
a fast or slow current decay to be used
in the driver.
The digital comparator compares
each new value with the previous one
and the value for the preset level for fast
current decay. If the new value is strictly
lower than both of the others, a fast
current decay condition exists. The flip
flop sets the CD output. The CD output
is updated each time a new value is
loaded into the D/A register. The fast
current decay signals are used by the
driver circuit, PBL 3771/1, to change the
current control scheme of the output
stages. This is to avoid motor current
dragging which occurs at high stepping
rates and during the negative current
slopes, as illustrated in figure 9. Eight
Output
Output
Output
Actual
Gain
error
Correct
Endpoint
non-linearity
More
than 2
bits
Less
than 2
bits
Negative
difference
Positive
difference
Offset error
Full scale
Input
Input
Input
Figure 5. Errors in D/A conversion.
Differential non-linearity of more than 1
bit, output is non-monotonic.
Figure 6. Errors in D/A conversion.
Differential non-linearity of less than 1 bit,
output is monotonic.
Figure 7. Errors in D/A conversion. Non-
linearity, gain and offset errors.
5
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