IBM0418166XLAC-50 datasheet, PDF

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IBM0418166XLAC-50: DescriptionStandard SRAM, 1MX18, 2.25ns, CMOS, PBGA119, 17 X 7 MM, BGA-119; Categorystorage storage; File Size265KB，25 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM0418166XLAC-50 Overview

Standard SRAM, 1MX18, 2.25ns, CMOS, PBGA119, 17 X 7 MM, BGA-119

IBM0418166XLAC-50 Parametric

Parameter Name	Attribute value
Maker	IBM
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	2.25 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	18874368 bi
Memory IC Type	STANDARD SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	1MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.679 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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Preliminary

IBM0436166XLAC

IBM0418166XLAC

16Mb (512K x 36 & 1M x 18) SRAM

Features

• 512K

36 or 1M

18 organization

• CMOS technology

• Synchronous pipeline mode of operation with

self-timed late write

• Single differential HSTL clock

• HSTL input and output levels

• +2.5V power supply

• Registered addresses, write enables, synchro-

nous select, and data-ins

• Common I/O

• Asynchronous output enable and sleep mode

inputs

• Boundary scan using a limited set of JTAG

1149.1 functions

• Byte write capability and global write enable

• 7

17 bump ball grid array (BGA) package with

SRAM JEDEC standard pinout and boundary

scan order

• Programmable impedance output drivers

Description

The IBM0418166XLAC and IBM0436166XLAC

16Mb SRAM

are synchronous pipeline mode, high-

performance CMOS static random-access memo-

ries that have wide I/O and achieve 2-ns cycle times.

Single differential K clocks are used to initiate the

read/write operation, and all internal operations are

self-timed. At the rising edge of the K clock, all

addresses, write enables, synchronous selects, and

data-ins are registered internally. Data-outs are

updated from output registers off the next rising

edge of the K clock. An internal write buffer allows

write data to follow one cycle after addresses and

controls. The chip is operated with a single +2.5V

power supply and is compatible with HSTL I/O inter-

faces.

XLACds.fm.00

November 24, 2003

Page 1 of 25

IBM0418166XLAC-50 Related Products

	IBM0418166XLAC-50	IBM0418166XLAC-40	IBM0418166XLAC-30
Description	Standard SRAM, 1MX18, 2.25ns, CMOS, PBGA119, 17 X 7 MM, BGA-119	Standard SRAM, 1MX18, 2ns, CMOS, PBGA119, 17 X 7 MM, BGA-119	Standard SRAM, 1MX18, 1.5ns, CMOS, PBGA119, 17 X 7 MM, BGA-119
Maker	IBM	IBM	IBM
Parts packaging code	BGA	BGA	BGA
package instruction	BGA,	BGA,	BGA, BGA119,7X17,50
Contacts	119	119	119
Reach Compliance Code	unknow	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A

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