IBM043611TLAB-6 datasheet, PDF

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IBM043611TLAB-6: DescriptionStandard SRAM, 32KX36, 3ns, CMOS, PBGA119, BGA-119; Categorystorage storage; File Size320KB，22 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM043611TLAB-6 Overview

Standard SRAM, 32KX36, 3ns, CMOS, PBGA119, BGA-119

IBM043611TLAB-6 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IBM
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	unknow
ECCN code	3A991.B.2.A
Maximum access time	3 ns
Maximum clock frequency (fCLK)	166.66 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	1179648 bi
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5,3.3 V
Certification status	Not Qualified
Maximum seat height	2.41 mm
Maximum standby current	0.025 A
Minimum standby current	3.14 V
Maximum slew rate	0.375 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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IBM043611TLAB4M x 1612/10, 3.3VMMDM15DSU-021045122.

Preliminary

Features

• 32K x 36 or 64K x 18 Organizations

• 0.45 Micron CMOS Technology

• Synchronous Pipeline Mode of Operation with

Self-Timed Late Write

• Single Differential HSTL/GTL Clock

• Single +3.3V Power Supply and Ground

• HSTL/GTL Input and Output levels

• Registered Addresses, Write Enables, Synchro-

nous Select, and Data Ins

• Registered Outputs

IBM041811TLAB

IBM043611TLAB

32K x 36 & 64K x 18 SRAM

• Common I/O

• Asynchronous Output Enable and Power Down

Inputs

• Boundary Scan using limited set of JTAG 1149.1

functions

• Byte Write Capability & Global Write Enable

• 7 x 17 Bump Ball Grid Array Package with

SRAM EDEC Standard Pinout and Boundary

SCAN Order

• Programmable Impedance Output Drivers

Description

The IBM043611TLAB and IBM041811TLAB 1Mb

SRAM

are Synchronous Pipeline Mode, high-per-

formance CMOS Static Random Access Memories

that are versatile, have wide I/O, and achieve 4ns

cycle times. Dual differential K clocks are used to ini-

tiate the read/write operation, and all internal opera-

tions are self-timed. At the rising edge of the K clock,

all Addresses, Write-Enables, Sync Select, and

Data Ins are registered internally. Data Outs are

updated from output registers off the next rising

edge of the K clock. An internal Write buffer allows

write data to follow one cycle after addresses and

controls. The chip is operated with a single +3.3V

power supply and is compatible with HSTL/GTL I/O

interfaces.

77H9965.T5

10/98

Use is further subject to the provisions at the end of this document.

Page 1 of 22

IBM041811TLAB

IBM043611TLAB

32K x 36 & 64K x 18 SRAM

Preliminary

SRAM Features

Late Write

Late Write function allows for write data to be registered one cycle after addresses and controls. This feature

eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is

accomplished by buffering write addresses and data so that the write operation occurs during the next write

cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-

rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be

updated with address and data from the holding registers. Read cycle addresses are monitored to determine

if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array

occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last

written address will have new byte data from the write buffer and remaining bytes from the SRAM array.

Mode Control

Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. The SRAM

supports the following protocols:

• Single Clock, Flow-Through (M1 = V

, M2 = V

)

• Pipeline (M1 = V

, M2 = V

)

• Register-Latch (M1 = V

, M2 = V

)

• Dual Clock, Flow-Through (M1 = V

, M2 = V

)

This datasheet only describes Pipeline functionality. Mode control inputs must be set with power-up and must

not change during SRAM operation. Dual Clock will not be offered.

Sleep Mode

Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep mode, the

outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a

recovery time (t

ZZR

) is required before the SRAM resumes to normal operation.

Programmable Impedance/Power-Up Requirements

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to allow for the

SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line

impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a toler-

ance of TBD% is between 175W and 350W. Periodic readjustment of the output driver impedance is neces-

sary as the impedance is greatly affected by drifts in supply voltage and temperature. One evaluation occurs

every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a

time towards the optimum level. The output driver has 32 discrete binary weighted steps. The impedance

update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchro-

nously switch the SRAM into and out of High-Z, triggering an update. The user may choose to invoke asyn-

chronous G updates by providing a G setup and hold about the K Clock to guarantee the proper update. In

order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time

after V

reaches its operating range. Furthermore, 2048 cycles followed by a Low-Z to High-Z transition are

required to guarantee optimum output driver impedance.

Use is further subject to the provisions at the end of this document.

77H9965.T5

10/98

Page 4 of 22

IBM043611TLAB-6 Related Products

	IBM043611TLAB-6	IBM043611TLAB-4N	IBM043611TLAB-5	IBM043611TLAB-7	IBM043611TLAB-4
Description	Standard SRAM, 32KX36, 3ns, CMOS, PBGA119, BGA-119	Standard SRAM, 32KX36, 2.25ns, CMOS, PBGA119, BGA-119	Standard SRAM, 32KX36, 2.5ns, CMOS, PBGA119, BGA-119	Standard SRAM, 32KX36, 3ns, CMOS, PBGA119, BGA-119	Standard SRAM, 32KX36, 2.1ns, CMOS, PBGA119, BGA-119
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	IBM	IBM	IBM	IBM	IBM
Parts packaging code	BGA	BGA	BGA	BGA	BGA
package instruction	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50
Contacts	119	119	119	119	119
Reach Compliance Code	unknow	unknown	unknown	unknow	unknow
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	3 ns	2.25 ns	2.5 ns	3 ns	2.1 ns
Maximum clock frequency (fCLK)	166.66 MHz	232.55 MHz	200 MHz	142.85 MHz	250 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
JESD-609 code	e0	e0	e0	e0	e0
length	22 mm	22 mm	22 mm	22 mm	22 mm
memory density	1179648 bi	1179648 bit	1179648 bit	1179648 bi	1179648 bi
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	36	36	36	36	36
Number of functions	1	1	1	1	1
Number of terminals	119	119	119	119	119
word count	32768 words	32768 words	32768 words	32768 words	32768 words
character code	32000	32000	32000	32000	32000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32KX36	32KX36	32KX36	32KX36	32KX36
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.41 mm	2.41 mm	2.41 mm	2.41 mm	2.41 mm
Maximum standby current	0.025 A	0.025 A	0.025 A	0.025 A	0.025 A
Minimum standby current	3.14 V	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	0.375 mA	0.55 mA	0.5 mA	0.35 mA	0.55 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm	14 mm	14 mm

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