PEEL16V8SL-25 datasheet, PDF - EEWORLD Datasheet

PEEL16V8SL-25: DescriptionEE PLD, 25ns, PAL-Type, CMOS, PDSO20, SOIC-20; CategoryProgrammable logic devices Programmable logic; File Size633KB，10 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PEEL16V8SL-25 Overview

EE PLD, 25ns, PAL-Type, CMOS, PDSO20, SOIC-20

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	SOIC
package instruction	SOP, SOP20,.4
Contacts	20
Reach Compliance Code	unknow
Other features	8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Architecture	PAL-TYPE
maximum clock frequency	37 MHz
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
Dedicated input times	8
Number of I/O lines	8
Number of entries	18
Output times	8
Number of product terms	64
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm

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