IS61LPS12832EC-250B2L datasheet, PDF

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IS61LPS12832EC-250B2L: DescriptionCache SRAM, 128KX32, 2.6ns, CMOS, PBGA119, BGA-119; Categorystorage storage; File Size2MB，36 Pages; ManufacturerIntegrated Silicon Solution ( ISSI ); Environmental Compliance

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IS61LPS12832EC-250B2L Overview

Cache SRAM, 128KX32, 2.6ns, CMOS, PBGA119, BGA-119

IS61LPS12832EC-250B2L Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	2.6 ns
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	4194304 bi
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum standby current	0.08 A
Minimum standby current	3.14 V
Maximum slew rate	0.235 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	10
width	14 mm

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IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC

IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC

128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT SRAM

APRIL 2014

FEATURES



Internal self-timed write cycle

Individual Byte Write Control and Global Write

Clock controlled, registered address, data and

control

Burst sequence control using MODE input

Three chip enable option for simple depth

expansion and address pipelining

Common data inputs and data outputs

Auto Power-down during deselect

Single cycle deselect

Snooze MODE for reduced-power standby

JEDEC 100-pin QFP, 165-ball BGA and 119-

ball BGA packages

Power supply:

LPS: V

3.3V (± 5%), V

DDQ

3.3V/2.5V (± 5%)

VPS: V

2.5V (± 5%), V

DDQ

2.5V (± 5%)



JTAG Boundary Scan for BGA packages

Industrial and Automotive temperature support

Lead-free available

Error Detection and Error Correction

Write cycles are internally self-timed and are initiated

by the rising edge of the clock input. Write cycles can

be one to four bytes wide as controlled by the write

control inputs.

Separate byte enables allow individual bytes to be

written. The byte write operation is performed by using

the byte write enable (/BWE) input combined with one

or more individual byte write signals (/BWx). In

addition, Global Write (/GW) is available for writing all

bytes at one time, regardless of the byte write controls.

Bursts can be initiated with either /ADSP (Address

Status Processor) or /ADSC (Address Status Cache

Controller) input pins. Subsequent burst addresses can

be generated internally and controlled by the /ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence

order. Linear burst is achieved when this pin is tied

LOW. Interleave burst is achieved when this pin is tied

HIGH or left floating

DESCRIPTION

The 4Mb product family features high-speed, low-

power synchronous static RAMs designed to provide

burstable, high-performance memory for

communication and networking applications. The

IS61(64)LPS/VPS12836EC

are organized as

131,072

words

by 36bits. The

IS61(64)LPS/VPS12832EC

are organized as

131,072

words by 32bits. The

IS61(64)LPS/VPS25618EC

are

organized as

262,144

words by 18 bits. Fabricated with

ISSI's advanced CMOS technology, the device

integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single

monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single

clock input.

FAST ACCESS TIME

Symbol

MAX

Parameter

Clock Access Time

Cycle time

Frequency

-250

2.6

250

-200

3.1

200

Units

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such

applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.- www.issi.com

Rev. C

03/19/2014

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