Intel StrataFlash
®
Embedded Memory (P33)
Datasheet
Product Features
High performance:
— 85 ns initial access
— 52MHz with zero wait states, 17ns clock-to-
data output synchronous-burst read mode
— 25 ns asynchronous-page read mode
— 4-, 8-, 16-, and continuous-word burst mode
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 3.0 V buffered programming at 7 µs/byte
(Typ)
Architecture:
— Multi-Level Cell Technology: Highest Density
at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte main blocks
Voltage and Power:
— V
CC
(core) voltage: 2.3 V – 3.6 V
— V
CCQ
(I/O) voltage: 2.3 V – 3.6 V
— Standby current: 35µA (Typ) for 64-Mbit
— 4-Word synchronous read current:
16 mA (Typ) at 52MHz
Quality and Reliability
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology
Security:
— One-Time Programmable Registers:
— 64 unique factory device identifier bits
— 2112 user-programmable OTP bits
— Selectable OTP space in Main Array:
— Four pre-defined 128-KByte blocks (top or
bottom configuration).
— Up to Full Array OTP Lockout
— Absolute write protection: V
PP
= V
SS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down capability
Software:
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel
®
Flash Data Integrator optimized
— Basic Command Set and Extended Command
Set compatible
— Common Flash Interface capable
Density and Packaging
— 56-Lead TSOP package (64, 128, 256, 512-
Mbit)
— 64-Ball Intel® Easy BGA package (64, 128,
256, 512-Mbit)
— Intel® QUAD+ SCSP (64, 128, 256, 512-Mbit)
— 16-bit wide data bus
Order Number: 314749-004
November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal L ines and D isc laim er s
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at
http://www.intel.com.
Intel the Intel logo, Intel StrataFlash, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Intel Corporation. All Rights Reserved.
Datasheet
2
November 2007
Order Number: 314749-004
Intel StrataFlash
®
Embedded Memory P33
Contents
1.0
Introduction
.............................................................................................................. 6
1.1
Nomenclature ..................................................................................................... 6
1.2
Acronyms........................................................................................................... 6
1.3
Conventions ....................................................................................................... 7
Functional Overview
.................................................................................................. 8
2.1
Virtual Chip Enable Description.............................................................................. 8
Package Information
............................................................................................... 10
3.1
56-Lead TSOP................................................................................................... 10
3.2
64-Ball Easy BGA Package .................................................................................. 12
3.3
QUAD+ SCSP Packages ...................................................................................... 14
Ballout and Signal Descriptions
............................................................................... 17
4.1
Signal Ballout ................................................................................................... 17
4.2
Signal Descriptions ............................................................................................ 20
4.3
Dual Die SCSP Configurations ............................................................................. 23
4.4
Memory Maps ................................................................................................... 24
Maximum Ratings and Operating Conditions............................................................
27
5.1
Absolute Maximum Ratings................................................................................. 27
5.2
Operating Conditions ......................................................................................... 28
Electrical Specifications
........................................................................................... 29
6.1
DC Current Characteristics.................................................................................. 29
6.2
DC Voltage Characteristics.................................................................................. 31
AC Characteristics
................................................................................................... 32
7.1
AC Test Conditions ............................................................................................ 32
7.2
Capacitance...................................................................................................... 33
7.3
AC Read Specifications....................................................................................... 34
7.4
AC Write Specifications ...................................................................................... 40
7.5
Program and Erase Characteristics....................................................................... 43
Power and Reset Specifications
............................................................................... 44
8.1
Power-Up and Power-Down................................................................................. 44
8.2
Reset Specifications........................................................................................... 44
8.3
Power Supply Decoupling ................................................................................... 45
Device Operations
................................................................................................... 46
9.1
Bus Operations ................................................................................................. 46
9.1.1 Reads ................................................................................................... 46
9.1.2 Writes................................................................................................... 46
9.1.3 Output Disable ....................................................................................... 47
9.1.4 Standby ................................................................................................ 47
9.1.5 Reset.................................................................................................... 47
9.2
Device Commands............................................................................................. 47
9.3
Command Definitions......................................................................................... 49
Operations
...................................................................................................... 51
Asynchronous Page-Mode Read ........................................................................... 51
Synchronous Burst-Mode Read............................................................................ 51
Read Configuration Register................................................................................ 52
10.3.1 Read Mode ............................................................................................ 53
10.3.2 Latency Count........................................................................................ 53
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0 Read
10.1
10.2
10.3
November 2007
Order Number: 314749-004
Datasheet
3
Intel StrataFlash
®
Embedded Memory P33
10.3.3 WAIT Polarity .........................................................................................55
10.3.4 Data Hold ..............................................................................................56
10.3.5 WAIT Delay............................................................................................57
10.3.6 Burst Sequence ......................................................................................57
10.3.7 Clock Edge.............................................................................................57
10.3.8 Burst Wrap ............................................................................................58
10.3.9 Burst Length ..........................................................................................58
10.3.10 End of Word Line (EOWL) Considerations ...................................................58
11.0 Programming Operations
.........................................................................................59
11.1 Word Programming ............................................................................................59
11.1.1 Factory Word Programming......................................................................60
11.2 Buffered Programming .......................................................................................60
11.3 Buffered Enhanced Factory Programming ..............................................................61
11.3.1 BEFP Requirements and Considerations .....................................................61
11.3.2 BEFP Setup Phase ...................................................................................62
11.3.3 BEFP Program/Verify Phase ......................................................................62
11.3.4 BEFP Exit Phase......................................................................................63
11.4 Program Suspend ..............................................................................................63
11.5 Program Resume ...............................................................................................63
11.6 Program Protection ............................................................................................64
12.0 Erase Operations......................................................................................................65
12.1 Block Erase .......................................................................................................65
12.2 Erase Suspend ..................................................................................................65
12.3 Erase Resume ...................................................................................................66
12.4 Erase Protection ................................................................................................66
13.0 Security Modes
........................................................................................................67
13.1 Block Locking ....................................................................................................67
13.1.1 Lock Block .............................................................................................67
13.1.2 Unlock Block ..........................................................................................67
13.1.3 Lock-Down Block ....................................................................................68
13.1.4 Block Lock Status ...................................................................................68
13.1.5 Block Locking During Suspend ..................................................................68
13.2 Selectable One-Time Programmable Blocks ...........................................................69
13.2.1 Permanent Block Locking of up to 512 KB ..................................................69
13.2.2 Permanent Block Locking of up to Full Main Array........................................70
13.3 Protection Registers ...........................................................................................71
13.3.1 Reading the Protection Registers...............................................................72
13.3.2 Programming the Protection Registers .......................................................72
13.3.3 Locking the Protection Registers ...............................................................72
14.0 Special Read States..................................................................................................73
14.1 Read Status Register..........................................................................................73
14.1.1 Clear Status Register ..............................................................................74
14.2 Read Device Identifier ........................................................................................74
14.3 CFI Query .........................................................................................................75
A
B
C
D
E
F
Write State Machine.................................................................................................76
Flowcharts
...............................................................................................................83
Common Flash Interface
..........................................................................................92
Additional Information...........................................................................................
102
Ordering Information for Discrete Products
........................................................... 103
Ordering Information for SCSP Products
................................................................ 104
Datasheet
4
November 2007
Order Number: 314749-004
Intel StrataFlash
®
Embedded Memory P33
Date
April 2006
August 2006
Revision
001
002
Description
Initial release
Product release
Update and provide general document clarifications
Revise ICCR values for Page-Mode Read
Added note for V
ccq
change on TSOP burst operation
Added TSOP Burst AC Read specification
Updated new revision of CFI
Updated Flowcharts
Updated description of Burst Operation
Document changes regarding burst operation with the TSOP package.
Updated for 65nm lithography.
Define W602 Erase to Suspend.
May 2007
003
October 2007
004
November 2007
Order Number: 314749-004
Datasheet
5
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