PRELIMINARY
CY28447
Clock Generator for Intel
®
Calistoga Chipset
Features
• Compliant to Intel
®
CK410M
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
CLKREQ#[1:9]
• 96/100 MHz spreadable differential video clock
CPU
x2 / x3
SRC
x9/11
PCI
x5
REF
x2
DOT96
x1
USB_48M
x1
LCD
x1
27M
x2
• 33 MHz PCI clocks
• Buffered Reference Clock 14.318MHz
• Low-voltage frequency select inputs
• I
2
C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 72-pin QFN package
Block Diagram
XIN
XOUT
SEL_CLKREQ
PCI_STP#
CPU_STP#
CLKREQ[1:9]#
ITP_SEL
FS[C:A]
14.318M
Hz
Crystal
VDD
REF[1:0]
IREF
VDD
CPUT[0:1]
CPUC[0:1]
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD
SRCT(1:9])
SRCC(1:9])
VDD
PCI[1:4]
VDD_PCI
PCIF0
VDD
SRCT0/100M
T_SST
SRCC0/100M
C_SST
VDD48
27MSpread
VDD48
DOT96T
DOT96C
VDD48
48M
27M
PLL
VTT_PW
RGD#/PD
SDATA
SCLK
I2C
Logic
Pin Configuration
CLKREQ9#
CLKREQ8#
SRCT_8
SRCC_8
VSS_SRC
SRCC_7
SRCT_7
VDD_SRC
SRCC_6
SRCT_6
CLKREQ6#
SCRC_5
SRCT_5
SCRC_4
SRCT_4
CLKREQ4#
SRCC_3
SRCT_3
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
PLL Reference
CPU
PLL
Divider
LVDS
PLL
FCTSEL1
Divider
VDD_SRC
SRCC_9
SRCT_9
VSS_SRC
CPUC2_ITP / SRCC_10
CPUT2_ITP / SRCT_10
VDDA
VSSA
IREF
CPUC1
CPUT1
VDD_CPU
CPUC0
CPUT0
VSS_CPU
SCLK
SDATA
VDD_REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54
53
52
51
50
49
48
47
CY28447
46
45
44
43
42
41
40
39
38
37
VDD_SRC
SRCC_2
SRCT_2
SRCC_1
SRCT_1
VDD_SRC
SRCC_0 / LCD100MC
SRCT_0 / LCD100MT
CLKREQ1#
FSB/TEST_MODE
DOT96C / 27M_SS
DOT96T / 27M_NSS
VSS_48
48M / FSA
VDD_48
VTT_PWRGD# / PD
CLKREQ7#
PCIF0/ITP_SEL
Divider
Divider
VDD48
27MNon-spread
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
XOUT
XIN
VSS_REF
REF1
REF0 / FSC_TEST_SEL
CPU_STP#
PCI_STP#
CLKREQ2#
PCI1
CLKREQ3#
CLKREQ5#
VDD_PCI
VSS_PCI
PCI2
PCI3
PCI4 / FCTSEL1
VSS_PCI
VDD_PCI
Fixed
PLL
Page 1 of 21
www.SpectraLinear.com
CY28447
Pin Description
Pin No.
2, 3, 50, 51,
52, 53, 55,
56, 58, 59,
60, 61, 63,
64, 66, 67,
69, 70
4, 68
5, 6
Name
SRCT/C[1:9]
Type
PWR
3.3V power supply for outputs.
Description
1, 49, 54, 65 VDD_SRC
O, DIF
100 MHz Differential serial reference clocks.
VSS_SRC
GND
Ground for outputs.
CPUT2_ITP/SRCT10, O, DIF
Selectable differential CPU or SRC clock output.
CPUC2_ITP/SRCC10
ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10
ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2
VDDA
VSSA
IREF
PWR
GND
I
3.3V power supply for PLL.
Ground for PLL.
A precision resistor is attached to this pin which is connected to the internal
current reference.
3.3V power supply for outputs.
Ground for outputs.
SMBus-compatible SCLOCK.
3.3V power supply for outputs.
14.318 MHz crystal input.
Ground for outputs.
Fixed 14.318 MHz clock output.
7
8
9
10, 11, 13, 14 CPUT/C[0:1]
12
15
16
17
18
19
20
21
22
23
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
REF1
O, DIF
Differential CPU clock outputs.
PWR
GND
I
PWR
I
GND
O
I/O, OD
SMBus-compatible SDATA.
O, SE
14.318 MHz crystal output.
REF0/FSC_TESTSEL I/O,PD
Fixed 14.318 clock output
/
3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to V
IMFS_C
when VTT_PWRGD# is
asserted LOW.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifi-
cations.
CPU_STP#
PCI_STP#
CLKREQ[1:9]#
I, PU
I, PU
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
3.3V LVTTL input for PCI_STP# active LOW.
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
24
25
26, 28, 29,
38, 46, 57,
62, 71, 72
27, 32, 33
30, 36
31, 35
34
PCI[1:3]
VDD_PCI
VSS_PCI
PCI4/FCTSEL1
O, SE
33 MHz clock outputs
PWR
GND
3.3V power supply for outputs.
Ground for outputs.
I/O, PD
33 MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on the VTT_PWRGD# assertion).
FCTS E L1 P in 43
0 DOT96T
1 27M_NSS
P in 44
DOT96C
27M_SS
P in 47
SRCT0
P in 48
SRCC0
96/100M_T 96/100M_C
37
ITP_SEL/PCIF0
I/O, PD,
3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output.
SE
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC10
Rev 1.0, November 20, 2006
Page 2 of 21
CY28447
Pin Description
(continued)
Pin No.
39
Name
VTT_PWRGD#/PD
Type
I, PD
Description
3.3V LVTTL input.
This pin is a level sensitive strobe used to latch the FSA, FSB,
FSC, FCTSEL1, and ITP_SEL. After VTT_PWRGD# (active LOW) assertion, this
pin becomes a real-time input for asserting power down (active HIGH).
3.3V power supply for outputs.
Fixed 48-MHz clock output / 3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
40
41
42
43, 44
45
VDD_48
48M/FSA
VSS_48
DOT96T/ 27M_NSS
DOT96C/ 27M_SS
FSB/TEST_MODE
PWR
I/O
GND
O, DIF
Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output
Selected via FCTSEL1 at VTTPWRGD# assertion.
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state
when in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47, 48
SRC[T/C]0/
LCD100M[T/C]
O,DIF
100 MHz differential serial reference clock output / Differential 96/100-MHz
SS clock for flat-panel display
Selected via FCTSEL1 at VTTPWRGD# assertion.
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 1. Frequency Select Table FSA, FSB, and FSC
[1]
FSC
1
0
0
0
.
FSB
0
0
1
1
FSA
1
1
1
0
CPU
100 MHz
133 MHz
166 MHz
200 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Note:
1. 27-MHz and 96-MHz can not be output at the same time.
Rev 1.0, November 20, 2006
Page 3 of 21
CY28447
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
46
....
....
....
....
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
46:39
47
55:48
56
....
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 20, 2006
Page 4 of 21
CY28447
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
/LCD_96_100M[T/C]
Description
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0 / LCD_96_100M[T/C] Output Enable
0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Name
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Description
27M NSS / DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB_48MHz
REF0
REF1
CPU[T/C]1
CPU[T/C]0
CPU, SRC, PCI, PCIF
Spread Enable
USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI4
PCI3
PCI2
PCI1
Reserved
Reserved
CPU[T/C]2
Reserved
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
Reserved, Set = 1
Reserved, Set = 1
CPU[T/C]2 Output Enable
0 = Disabled (Hi-Z), 1 = Enabled
Reserved, Set = 1
Description
Rev 1.0, November 20, 2006
Page 5 of 21
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
