1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
Features
• Operating frequency: 125 MHz to 500 MHz
• Supports DDRII SDRAM
• 1 to 10 differential clock buffer (SSTL_18)
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): 40 ps
• Very low output-to-output skew: 40 ps
• Auto power-down feature when input is low
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-8)
• 52-ball BGA
distributes a differential clock input pair (CK, CK#) to ten differ-
ential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential
pair of feedback clock outputs (FBOUT, FBOUT#).
The input clocks (CK, CK#), the feedback clocks (FBIN,
FBIN#), the LVCMOS (OE, OS), and the analog power input
(AVDD) control the clock outputs.
The PLL in the CY2SSTU877 clock driver uses the input
clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to
provide high-performance, low-skew, low-jitter output differ-
ential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able
to track Spread Spectrum Clocking (SSC) for reduced EMI.
When AVDD is grounded, the PLL is turned off and bypassed
for test purposes. When both clock signals (CK, CK#) are logic
low, the device will enter a low-power mode. An input logic
detection circuit on the differential inputs, independent from
the input buffers, will detect the logic low level and perform a
low-power state where all outputs, the feedback, and the PLL
are OFF. When the inputs transition from both being logic low
to being differential signals, the PLL will be turned back on, the
inputs and outputs will be enabled and the PLL will obtain
phase lock between the feedback clock pair (FBIN, FBIN#)
and the input clock pair (CK, CK#) within the specified stabili-
zation time t
L
.
Functional Description
The CY2SSTU877 is a high-performance, low-skew, low-jitter
zero delay buffer designed to distribute differential clocks in
high-speed applications.
This phase-locked loop (PLL) clock buffer is designed for a
V
DD
of 1.8V, an AV
DD
of 1.8V and SSTL18 differential data
input and output levels. This device is a zero delay buffer that
Block Diagram
Pin Configuration
1
A
B
C
D
E
F
G
H
J
K
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
52 BGA
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 8
www.SpectraLinear.com
CY2SSTU877
Pin Description
Pin No.
G1
H1
E1, F1
E6, F6
H6, G6
AGND
AVDD
FB_INT, FB_INC
FB_OUTT,
FB_OUTC
Name
1.8V analog supply
Feedback differential clock input
Feedback differential clock output
Ground
Output enable (ASYNC) for CLKT[0:9] and CLKC [0:9]
Output Select (Tied to GND or VDDQ)
1.8V supply
Buffered output of input clock, CLK
Buffered output of input clock, CLK
Description
Ground for 1.8V analog supply
CLK_INT, CLK_INC Differential clock input with a (10K–100K ) pull-down resistor
B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, GND
J5
F5
D5
D2, D3, D4, E2, E5, F2, G2, G3, G4, G5
A2, A1, D1, J1, K3, A5, A6, D6, J6, K4,
A3, B1, C1, K1, K2, A4, B6, C6, K6, K5
Table 1. Function Table
Inputs
AVDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
X
OE
H
H
L
L
L
L
H
H
X
X
OS
X
X
H
L
H
L
X
X
X
X
CLK_INT CLK_INC
L
H
L
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
L
H
OE
OS
VDDQ
CLKT [0:9]
CLKC [0:9]
Outputs
CLKT
L
H
Lz
Lz,CLKT7
Active
Lz
Lz,CLKT7
Active
L
H
Lz
CLKC
H
L
Lz
Lz,CLKC7
Active
Lz
Lz,CLKC7
Active
H
L
Lz
FB_OUTT FB_OUTC
L
H
L
H
L
H
L
H
Lz
Reserved
H
L
H
L
H
L
H
L
Lz
PLL
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
On
On
On
On
Off
Recommended Operating Conditions
Parameter
T
A
(Com.)
V
DD
, AV
DD
Description
Ambient Operating Temp
Operating Voltage
Condition
Min.
0
1.7
Max.
70
1.9
Unit
°C
V
Rev 1.0, November 21, 2006
Page 2 of 8
CY2SSTU877
Absolute Maximum Conditions
Parameter
V
IN
V
OUT
T
S
V
CC,
AV
CC
I
IK
I
OK
I
O
Description
Input Voltage Range
Output Voltage Range
Storage Temperature
Supply Voltage Range
Input Clamp Current
Output Clamp Current
Continuous Output Current
Continuous Current through V
DD
/GND
Condition
Min.
–0.5
–0.5
–65
–0.5
–50
–50
–50
–100
Max.
V
DDQ
+ 0.5
V
DDQ
+ 0.5
150
2.5
50
50
50
100
Unit
V
V
°C
V
mA
mA
mA
mA
DC Electrical Specifications
Parameter
V
IK
V
OD
V
OX
V
IX
V
ID
DC
V
ID
AC
V
IL
V
IH
V
OL
V
OH
I
IH
I
IL
I
ODL
I
DDLD
I
DD
I
OH
I
OL
C
IN
C
OUT
C
IN(DELTA)
Description
Input Clamping Voltage
Output Differential Voltage
Output Differential Crossing Voltage
Input Differential Crossing Voltage
Input Differential Voltage (DC Values)
Input Differential Voltage (AC Values)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input High Current
Input Low Current
Output disabled low current
Static Supply current
Dynamic Supply Current
Output High Current
Output Low Current
Input Capacitance
(Input Capacitance of
CLK_INT, CLK_INC,
FB_INT, FB_INC) V
I
=
V
DDQ
or GND
Ci(delta) (CLK_INT,
CLK_INC, FB_INT,
FB_INC) V
I
= V
DDQ
or
GND
2
(OE, OS, CLK_INT,
CLK_INC)
(OE, OS, CLK_INT,
CLK_INC)
I
OL
= 100 A
I
OL
= 9 mA
I
OH
= –100 A
I
OH
= –9 mA
V
IN
= V
DDQ
or GND
V
IN
= V
DDQ
or GND
V
ODL
= 100 mV
OE = GND
I
DDQ
+ I
ADD,
CLK_INT =
CLK_INC = GND
C
L
= 0 @ 270 MHz
V
DDQ
– 0.2
1.1
–250
–10
100
500
300
–9
9
3
250
10
0.65 * V
DDQ
0.1
0.6
Conditions
I
I
= –18 mA
0.5
V
DDQ
/2 – 0.08
(V
DDQ
/2) – 0.15
0.3
0.6
V
DDQ
/2 + 0.08
(V
DDQ
/2) + 0.15
V
DDQ
+ 0.4
V
DDQ
+ 0.4
0.35 * V
DDQ
Min.
Max.
–1.2
Unit
V
V
V
V
V
V
V
V
V
V
V
V
A
A
A
A
mA
mA
mA
pF
pF
–0.25
0.25
pF
Rev 1.0, November 21, 2006
Page 3 of 8
CY2SSTU877
AC Timing Specifications
Parameter
F
CLK[1,2]
T
DC
T
ODC
T
LOCK
T
OENB
T
ODIS
Tjitt (cc)
Tjit (Period)
Tjit (H-Period)
T
( )
T
( )DYN
T
SKEW
S
LR(O)
S
LR(I)
Description
Clock Frequency (Max)
Clock Frequency (Application)
Input Duty Cycle
Output Duty Cycle
PLL Lock Time
Output Enable Time
Output Disable Time
Cycle-to-cycle jitter
Period jitter
Half Period Cycle-to-cycle jitter
Static Phase Offset
Dynamic Phase Offset
Clock Skew
Output Slew Rate
Input Slew Rate
CLKT/ CLKC[0:9], FB_OUTT,
FB_OUTC
CLK_INT, CLK_INC, FB_INT,
FB_INC
OE
Above 270 MHz
Below 270 MHz
Average 1000 cycles
OE to any CLKT/ CLKC[0:9]
OE to any CLKT/ CLKC[0:9]
Conditions
Room temp and nominal V
DDQ
Room temp and nominal V
DDQ
Min.
125
250
40
48
–
–
–
–40
–30
–45
–60
–50
–40
–
1.5
1
0.5
Max.
500
500
60
52
15
8
8
40
30
45
60
50
40
40
4
4
Unit
MHz
MHz
%
%
s
ns
ns
ps
ps
ps
ps
ps
ps
ps
V/ns
V/ns
V/ns
Figure 1. Test Loads for Timing Measurement
Notes:
1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for
low speed system debug).
2. Application clock frequency indicates a range over which the PLL must meet all timing requirements.
Using CC2530, one as coordinator and one as terminal, point-to-point wireless communication, the terminal periodically sends data to the coordinator, and the coordinator prints the received data on th...
Unfortunately, the whole place is in English, so I came out confused... It's basically some cool designs made using LPC1100, and there is also a discussion area on it. [url]http://www.lpc1100challenge...
I have read the information about STR731 and that book, and found that I am now using an 8M external crystal oscillator, so the system can only work at a maximum of 8M, and the default setting at powe...
I am new to DSP. I want to know, when using DSP to implement digital filters, AD is needed to collect data. If it is an intermittent input signal, as shown in the attachment, how do I know that the co...
Recently, the first Digital China Summit was held in Fuzhou, attracting many domestic ICT industry giants to participate in the exhibition. The long queues outside the venue, the noisy and exciting...[Details]
When talking about Chinese chips, Ni Guangnan is indispensable. Let’s learn more about the relevant content with the embedded editor.
Since he co-founded Lenovo in 1985, Ni Guangnan has been s...[Details]
Profit growth of 85% in 2017, target revenue of 12.5 billion yuan in 2018: The company released its 2017 annual report, achieving revenue of 8.886 billion yuan, a year-on-year increase of 48.01%; prof...[Details]
Designing for automotive LCD displays larger than 5" can be complex. The display source driver requires a supply rail called analog voltage device drain (AVDD) in the 10V to 15V range and two supply ...[Details]
In order to strengthen the management of new energy vehicle charging facilities in our city, prevent and reduce accidents, protect the lives and property of the people, and improve the public safet...[Details]
introduction STM32 has many registers, which are difficult to remember, so the official packaged two sets of library functions. One is the standard library, but the official has not updated it on F7,...[Details]
Artificial intelligence
There is no inherent bias in AI. It does not "think" something is true or false for reasons that cannot be explained by logic. Unfortunately, human bias exists in mach...[Details]
This small program is still the use of timer, which is relatively simple. The specific parts are noted in the comments, please refer to the comments. /*********************************************...[Details]
Different from 51, AVR and other single-chip microcomputers, the clock signal sources of msp430 include LFXT1, XT2 and DCO. 1. LFXT1: It can connect high-speed and low-speed crystal oscillators. In l...[Details]
Kevin Jensen ams Semiconductor
Sensors
and lighting expert. Let's learn more about the relevant content with the network communication editor.
Everything is becoming "smart" these ...[Details]
On May 16, in response to
the public opinion storm caused by
Lenovo's
"
5G
voting" incident,
Lenovo
Holdings Chairman and
Lenovo
Group Founder Liu Chuanzhi, Lenovo Gr...[Details]
Site conditions: 1. AD acquisition, DMA transmission; AD is set to single-channel continuous mode, DMA is set to single-shot mode. The upper threshold of the AD analog watchdog setting is less than t...[Details]
I used the bit definition in my 51 program: bit flag. After defining it this way, I ran the program and downloaded it to the circuit board. I found that the flag was not the value I set, which led to...[Details]
The Vatican Secret Archives is one of the world's greatest historical collections, but many of its documents have never been transcribed. Recently, a project called Codice Ratio used a
combination...[Details]
I encountered a problem when debugging the STM32 system clock setting: TIM2 timing 1Ms, TIM2 interrupt service function time++, LED state changes when time=100. After the program runs, I found that t...[Details]
Automotive Electronics
京公网安备 11010802033920号
EEWORLD
