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LTC2205C

Description
IC 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X7 MM, PLASTIC, MO-220, QFN-48, Analog to Digital Converter
CategoryAnalog mixed-signal IC    converter   
File Size804KB,28 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric View All

LTC2205C Overview

IC 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X7 MM, PLASTIC, MO-220, QFN-48, Analog to Digital Converter

LTC2205C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN,
Contacts48
Reach Compliance Codecompli
ECCN codeEAR99
Maximum analog input voltage2.25 V
Minimum analog input voltage1.5 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N48
JESD-609 codee0
length7 mm
Maximum linear error (EL)0.0061%
Humidity sensitivity level3
Number of analog input channels1
Number of digits16
Number of functions1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Output bit codeOFFSET BINARY
Output formatPARALLEL, 8 BITS
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)255
Certification statusNot Qualified
Sampling rate65 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width7 mm
Electrical Specifications Subject to Change
FEATURES
LTC2205/LTC2204
16-Bit, 65Msps/40 Msps
ADCs
DESCRIPTIO
The LTC
®
2205/LTC2204 are sampling 16-bit A/D converters
designed for digitizing high frequency, wide dynamic range
signals up to input frequencies of 700MHz. The input range
of the ADC can be optimized with the PGA front end.
The LTC2205/LTC2204 are perfect for demanding com-
munications applications, with AC performance that in-
cludes 78dB SNR and 100dB spurious free dynamic range
(SFDR). Ultralow jitter of 120fs
RMS
allows undersampling
of high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.3V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycle.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Sample Rate: 65Msps/40Msps
79dB SNR and 100dB SFDR (2.25V Range)
SFDR >83dB at 170MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 530mW/470mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
105Msps: LTC2207 (16-Bit)
80Msps: LTC2206 (16-Bit)
65Msps: LTC2205 (16-Bit),
40Msps: LTC2204 (16-Bit)
48-Pin QFN Package
APPLICATIO S
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATIO
3.3V
SENSE
V
CM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
OV
DD
0.5V TO 3.3V
1µF
OF
CLKOUT
D15
D0
AIN
+
ANALOG
INPUT
AIN
+
S/H
AMP
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
V
DD
GND
ENC
ENC
PGA
SHDN
DITH
MODE
OE
RAND
1µF
1µF
3.3V
1µF
22076 TA01
ADC CONTROL INPUTS
U
U
U
22054p
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