CYS3C11CS-FREQ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > CYS3C11CS-FREQ

Preview

CYS3C11CS-FREQ: DescriptionQuartz Crystal Low Profile HC49S Leaded Crystal; File Size156KB，1 Pages; ManufacturerCrystek

Download Datasheet View All

CYS3C11CS-FREQ Overview

Quartz Crystal Low Profile HC49S Leaded Crystal

Preview

Download Datasheet

View All

Low Profile HC49S Leaded Crystal

Frequency Range:

Calibration Tolerance:

(Option)

Frequency Stability:

(Option)

Temperature Range:

(Option)

Storage:

Shunt Capacitance:

Drive Level:

ESR:

CYSxx Model

ree

dF S

Le oH ant

R pli

Quartz Crystal

3.180MHz to 40MHz (fund)

27MHz to 86MHz (3rd O/T)

±50ppm (Standard p/n)

±10ppm to ±100ppm

±100ppm (Standard p/n)

±10ppm to ±100ppm

0°C to 70°C (Standard p/n)

-20°C to 70°C

-40°C to 85°C

-55°C to 120°C

7.0pF Max

100uW Typical

see table 1

**Custom Designs Available

Standard part numbers

Part number

CY3DMS

CY3JS

CY3JMS

CY3JNS

CY3AS

CY3APS

CY4ES

CY4DS

CY7AS

CY7APS

CY5BS

CY6BS

CY6BPS

CY8GS

CY8GPS

CY9BS

CY12AS

CY11BS

CY11BPS

CY12BS

CY12BPS

CY14AS

CY14ACS

CY14APS

CY14BS

CY14BPS

CY15AS

CY16BS

CY16BPS

CY19AS

CY19BS

CY19BPS

CY20AS

CY20APS

CY22AS

CY22APS

CY24AS

CY24APS

CY25AS

Freq. (MHz)

3.579545

3.686400

4.000

4.194304

4.915200

5.000

5.0688

6.000

8.000

9.830400

10.000

11.059200

12.000

14.318180

14.745600

15.000

16.000

18.000

18.432

19.660800

20.000

24.000

25.000

18pF

series

18pF

20pF

series

20pF

12pF

series

20pF

series

20pF

series

20pF

series

20pF

series

20pF

series

18pF

20pF

series

20pF

series

20pF

series

20pF

series

20pF

series

20pF

series

20pF

series

Max ESR

150

120

100

Aging:

See

Options

0.150

(3.81)

0.019

(0.48)

0.183

(4.65)

<3ppm 1st/yr Max

Resistance at series resonance

Freq. (MHz)

3.18 - 3.4

3.5 - 4.0

4.1 - 4.9

5.0 - 5.9

6.0 - 11.9

12.0 - 14.9

15.0 - 30.0

30.1 - 86.0

Max ESR

190

150

120

100

0.400

(10.16)

0.440

(11.18)

0.192 ±0.005

(4.88 ±0.13)

Table 1

Dimensions inches (mm)

All dimensions are Max unless otherwise specified.

Build Your Own P/N

Frequency Tolerance

at 25°C

±10 ppm

±15 ppm

±20 ppm

±25 ppm

±30 ppm

±50 ppm

±100 ppm

CYS X X X X X - Freq

Frequency Stability

over Temp Range

Load

Capacitance

(-20 to 70°C)

(-40 to 85°C)

Series

14 pF

16 pF

18 pF

20 pF

22 pF

25 pF

32 pF

Options

Can Height (Max)

2.5mm

2.5mm w/ spacer

4.0mm

4.0mm w/ spacer

5.0mm

5.0mm w/ spacer

±10 ppm

(0 to 70°C)

±15 ppm

(0 to 70°C)

±20 ppm

(0 to 70°C)

±25 ppm

(0 to 70°C)

±30 ppm

(0 to 70°C)

±50 ppm

(0 to 70°C)

±100 ppm (0 to 70°C)

±15 ppm

(-20 to 70°C)

±20 ppm

(-20 to 70°C)

±30ppm

±50 ppm

±100 ppm

±20 ppm

±25 ppm

±30 ppm

±50 ppm

±100 ppm

Example:

CYS4F51CS-20.000 = ±25ppm at 25°C, ±50ppm 0 to 70°C, 20pF Load Cap, Fundamental,

5.0mm with Spacer, 20.000MHz

Mode

1 Fundamental 3.18-40 MHz

3 3rd Overtone 27-86 MHz

Specifications subject to change without notice.

TD-021005 Rev. C

Recommended Resources

Refrigerator compressor working principle circuit diagram

DM2-2500 type demagnetization switch control circuit

Automatic control compensator voltage starting circuit

Pulsating constant current charging circuit diagram

Hands-free phone automatic pick-up and hang-up device circuit diagram

±5--±20V slave tracking regulated power supply (the positive side is driven by the negative side)

Zigbeez: How many companies have mature solutions in smart home?: I want to build a smart home system using Zigbee technology. Are there many manufacturers like this? Which ones are good at it?...; sciencefor RF/Wirelessly

Help with FPGA and 2812 communication issues: I need help with the communication problem between two controllers. Explanation: Use XINTF for communication, FPGA sends 16-bit numbers to dsp data bus, dsp reads the data on the data bus through peri...; leejian113 FPGA/CPLD

Verilog problem with keypress: module key(clk,key_in,key_out); input clk; input[3:0]key_in;//key inputoutput[3:0]key_out; reg[3:0]dout1,dout2,dout3; reg[3:0]a; reg i; //assign key_out=a; always@(posedge clk)//key debounce begin dou...; hjl240 FPGA/CPLD

The task scheduling cycle of DM8168 is problematic. The simplest task will also intermittently have a scheduling cycle of about 335ms.: After the DM8168 system is started, only one main task is created, and only the following simple loop is performed in it, which is to continuously print the current execution time interval. Statistics...; yelo DSP and ARM Processors

I don't know if it's a hardware bug of stm32vet6Z: When USART3 is mapped in mode 2 (mapped to PD8, PD9), the AFIO function must be enabled first, and then the related peripherals must be initialized before USART is effective.The following code is corr...; mary1127 stm32/stm8

Testing the NXP USB C Multiport Adapter Evaluation Board's MCU: NXP USB C Multiport Adapter integrates a LPC11U35 Cortex-M0 MCU . MCU LPC11U35 is a core microcontroller responsible for the control of the entire system. Its main functions include the following part...; littleshrimp Integrated technical exchanges

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components