ZL50075GA datasheet, PDF - EEWORLD Datasheet

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ZL50075GA: DescriptionDigital Time Switch, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324; CategoryWireless rf/communication Telecom circuit; File Size744KB，53 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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ZL50075GA Overview

Digital Time Switch, PBGA324, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324

ZL50075GA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microsemi
Parts packaging code	BGA
package instruction	19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
Contacts	324
Reach Compliance Code	unknow
JESD-30 code	S-PBGA-B324
JESD-609 code	e0
length	19 mm
Number of functions	1
Number of terminals	324
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	1.9 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	DIGITAL TIME SWITCH
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	19 mm

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ZL50075

32 K Channel Digital Switch with High Jitter

Tolerance, Rate Conversion per Group of

2 Streams (8, 16, 32 or 64 Mbps),

and 64 Inputs and 64 Outputs

Data Sheet

Features

•

32,768 channel x 32,768 channel non-blocking

digital Time Division Multiplex (TDM) switch at

65.536 Mbps or 32.768 Mbps or using a

combination of rates

16,384 channel x 16,384 channel non-blocking

digital TDM switch at 16.384 Mbps

8,192 channel x 8,192 channel non-blocking

digital TDM switch at 8.192 Mbps

High jitter tolerance with multiple input clock

sources and frequencies

Up to 64 serial TDM input streams, divided into

32 groups with 2 input streams per group

64 serial TDM output streams, divided into 32

groups with 2 output streams per group

Per-group input and output data rate conversion

selection at 65.536 Mbps, 32.768 Mbps,

16.384 Mbps and 8.192 Mbps. Input and output

data group rates can differ

Per-stream input bit delay for flexible sampling

point selection

Per-stream output fractional bit advancement

Three sets of output timing signals for interfacing

additional devices

VDD_CORE

VDD_IO

VSS

January 2004

Ordering Information

ZL50075GA

3244 Ball PBGA

•

-40°C to +85°C

•

Per-channel A-Law/µ-Law Translation

Per-channel constant or variable throughput delay

for frame integrity and low latency applications

Per-stream Bit Error Rate (BER) test circuits

Per-channel high impedance output control

Per-channel force high output control

Per-channel message mode

Control interface compatible with Intel and

Motorola 16 bit non-multiplexed buses

Connection memory block programming

Supports ST-BUS and GCI-Bus standards for

input and output timing

IEEE 1149.1 (JTAG) test port

3.3 V I/O with 5V tolerant inputs; 1.8 V core

voltage

ODE

PWR

•

Input

Group 0

STiA0

STiB0

Data Memory

P/S

Converter

Output

Group 0

SToA0

SToB0

Input

Group 31

STiA31

STiB31

S/P

Converter

Connection Memory

SToA31

SToB31

Output

Timing

Output

Group 31

Input

Timing

FPi0

CKi0

CK_SEL1-0

FPo2-0

CKo2-0

Timing

Microprocessor Interface

and Control Registers

Test Access

Port

A18-0

DTA

WAIT

BERR

D15-0

TMS

TDi

TDo

TCK

Figure 1 - ZL50075 Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

R/W

SIZ1-0

D16B

TRST

ZL50075

Applications

•

Large Switching Platforms

Central Office Switches

Wireless Base Stations

Multi-service Access Platforms

Media Gateways

Data Sheet

Description

The ZL50075 is a maximum, 32,768 x 32,768 channel non-blocking Time Division Multiplex (TDM) switch. The

device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a

number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.

The ZL50075 has 64 input streams and 64 output data streams which can be programmed to operate at

8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full

32K x 32 K channel switching capacity at bit rates of 65 Mbps or 32 Mbps. Up to 32 input and output data streams

may operate at 65 Mbps. Up to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The

data rate can be independently set in groups of 2 input or output streams. In this way it is possible to provide rate

conversion from input data channel to output data channel.

The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary

and timing.

The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are

connected to multiple TDM components or circuits. These include:

•

Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams

connected through different data paths

Four timing outputs, CKo1 - 0 and FPo1 - 0, which can be configured independently to provide a variety of

clock and frame pulse options

Support of both ST-BUS and GCI-Bus formats

The ZL50075 also has a number of value added features for voice and data applications:

•

Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity

applications

Per-channel A-Law/µ-Law Conversions for voice

64 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated Bit

Error Rate (BER) test capability to facilitate data path integrity checking

The ZL50075 has two modes of operation: Connection Mode (normal) and Message Mode. In Connection Mode,

data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping controlled

by the Configuration Memory. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to

the output data streams on a per-channel basis. This feature is useful for transferring control and status information

to external circuits or other TDM devices.

A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and

Control Registers used to program ZL50075 options. The port is configurable to interface with either 16 bit Motorola

or Intel-type microprocessors.

The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

Zarlink Semiconductor Inc.

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