Ordering number : EN8297A
LC87F5JC8A
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The SANYO LC87F5JC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 83.3ns, integrates on a single chip a number of hardware features such as 128K byte flash ROM (onboard
programmable), 4096 byte RAM, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8-
bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with
a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-of-day
clock,
a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities),
an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD converter, two
12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 26-source 10-vector
interrupt feature.
Features
Flash
ROM
•
Capable of on-board-programing with wide range, 3.0 to 5.5V, of voltage source.
•
Block-erasable in 128 byte units
•
131072
×
8-bits (LC87F5JC8A)
RAM
•
4096
×
9-bits (LC87F5JC8A)
Minimum
Bus Cycle
•
83.3ns (12MHz)
VDD=3.0 to 5.5V
•
125ns (8MHz)
VDD=2.5 to 5.5V
•
500ns (2MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.05
20707HKIM 20060222-S00012 No.8297-1/25
LC87F5JC8A
Minimum
Instruction Cycle Time
•
250ns (12MHz)
VDD=3.0 to 5.5V
•
375ns (8MHz)
VDD=2.5 to 5.5V
•
1.5μs (2MHz)
VDD=2.2 to 5.5V
Ports
•
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
•
Normal withstand voltage input port
•
Dedicated oscillator ports
•
Reset pins
•
Power pins
46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
Timers
•
Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
×
2-channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2-channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8-bits can be used as PWM)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Timer 8: 16-bit timer
Mode 0: 8-bit timer with an 8-bit prescaler
×2-channels
Mode 1: 16-bit timer with an 8-bit prescaler
* Timer 8 is not supported in this version of Emulator. Please use on-chip-debugger for debugging when developing
software.
•
Base Timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-speed
Clock Counter
1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2. Can generate output real-time.
SIO
•
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.8297-2/25
LC87F5JC8A
UART
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit(2-bit in continuous data transmission)
•
Built-in baudrate generator
AD
Converter: 8-bit × 11-channels
PWM:
Multifrequency 12-bit PWM × 2-channels
Remote
Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
•
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog
Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Clock
Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
•
26 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer
T0H/INT6
T1L/T1H/INT7
SIO0/UART1 receive/T8L/T8H
SIO1/UART1 transmit
ADC/T6/T7
Port 0/T4/T5/PWM2, PWM3
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
•
IFLG (list of interrupt source flag function)
3) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the
diagram above).
Subroutine
Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed
Multiplication/Division Instructions
•
16-bits
×
8-bits
(5 tCYC execution time)
•
24-bits
×
16-bits
(12 tCYC execution time)
•
16-bits
÷
8-bits
(8 tCYC execution time)
•
24-bits
÷
16-bits
(12 tCYC execution time)
No.8297-3/25
LC87F5JC8A
Oscillation
Circuits
•
RC oscillation circuit (internal):
•
CF oscillation circuit:
•
Crystal oscillation circuit:
•
Frequency variable RC oscillation circuit (internal):
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
For system clock
System
Clock Divider Function
•
Can run on low current.
•
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base
timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
ROM
Correction Function
•
Executes the correction program on detection of a match with the program counter value.
•
Correction program area size: 128 bytes
On-chip
Debugger
•
Supports software debugging with the IC mounted on the target board.
Package
Form
•
QIP64E (14×14):
•
TQFP64J (10×10):
•
TQFP64J (7×7):
Development
Tools
•
Evaluation chip:
•
Emulator:
•
On-chip debugger:
Lead-free type
Lead-free type
Lead-free type
LC87EV690
EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP
ICE-B877300 + SUB875800 + POD64QFP or POD64SQFP
TCB87-TypeA or TCB87-TypeB+LC87F5JC8A
No.8297-4/25
LC87F5JC8A
Flash
ROM Programming Boards
Package
QIP64E (14×14)
TQFP64J (10×10)
TQFP64J (7×7)
Programming boards
W87F50256Q
W87F57256SQ
W87F58256TQ7
Flash
ROM Programmer
Maker
Flash Support Group, Inc.
(Formerly Ando Electric
Co., Ltd.)
Gang
Single
Model
AF9708/AF9709/
AF9709B
AF9723 (Main body)
AF9833 (Unit)
SANYO
SKK (Sanyo FWS)
After 02.04
After 01.84
After 1.02C (Install CD)
LC87F5JC8A
Supported version (Note)
After 02.40
Device
LC87F5JC8A FAST
Note: Please check the latest version.
No.8297-5/25
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