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FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 Watts Including I
DD
& I
REF
Midscale Preset, AD8802
Separate V
REFL
Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
FUNCTIONAL BLOCK DIAGRAM
CS
CLK
D7
AD8802/AD8804
DAC
1
DAC
REG
#1
D0
R
V
DD
V
REFH
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
D11
D10
D9
D8
D7
EN
ADDR
DEC
SER
REG
SDI
D
D0
D7
DAC
12
DAC
REG
#12
R
8
D0
SHDN
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
V
REFL
pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
GND
RS
(AD8802 ONLY)
V
REFL
(AD8804 ONLY)
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10
µA
from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10
µA
while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD8802/AD8804–SPECIFICATIONS
Parameter
STATIC ACCURACY
Specifications apply to all DACs
Resolution
Differential Nonlinearity Error
Integral Nonlinearity Error
Full-Scale Error
Zero Code Error
DAC Output Resistance
Output Resistance Match
REFERENCE INPUT
Voltage Range
2
REFH Input Resistance
REFL Input Resistance
3
Reference Input Capacitance
3
DIGITAL INPUTS
Logic High
Logic Low
Logic High
Logic Low
Input Current
Input Capacitance
3
POWER SUPPLIES
4
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Shutdown Current
Power Dissipation
Power Supply Sensitivity
DYNAMIC PERFORMANCE
3
V
OUT
Settling Time
Crosstalk
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS
Setup Time
CS
High Pulse Width
Reset Pulse Width
CLK Rise to
CS
Rise Hold Time
CS
Rise to Clock Rise Setup
Symbol
Conditions
N
DNL
INL
G
FSE
V
ZSE
R
OUT
∆R/R
O
V
REFH
V
REFL
R
REFH
R
REFL
C
REF0
C
REF1
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD
Range
I
DD
I
DD
I
REFH
P
DISS
PSRR
t
S
CT
t
CH
, t
CL
t
DS
t
DH
t
CSS
t
CSW
t
RS
t
CSH
t
CS1
(V
DD
= +3 V 10% or +5 V 10%, V
REFH
= +V
DD
, V
REFL
= 0 V, –40 C
≤T
A
≤
+85 C unless otherwise noted)
Min
Typ
1
Max
Units
Guaranteed Monotonic
8
–1
–1.5
–1
–1
3
±
1/4
±
1/2
1/2
1/4
5
1.5
+1
+1.5
+1
+1
8
Bits
LSB
LSB
LSB
LSB
kΩ
%
V
V
kΩ
kΩ
pF
pF
V
V
V
V
µA
pF
V
µA
mA
µA
µW
%/%
µs
dB
ns
ns
ns
ns
ns
ns
ns
ns
Pin Available on AD8804 Only
Digital Inputs = 55
H
, V
REFH
= V
DD
Digital Inputs = 55
H
, V
REFL
= V
DD
Digital Inputs all Zeros
Digital Inputs all Ones
V
DD
= +5 V
V
DD
= +5 V
V
DD
= +3 V
V
DD
= +3 V
V
IN
= 0 V or + 5 V
0
0
1.2
1.2
32
32
2.4
V
DD
V
DD
0.8
2.1
0.6
±
1
5
2.7
5.5
10
4
10
55
0.002
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= 2.4 V or V
IL
= 0.8 V, V
DD
= +5.5 V
SHDN
= 0
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V
V
DD
= +5 V
±
10%
±
1/2 LSB Error Band
Between Adjacent Outputs
5
Clock Level High or Low
15
5
5
10
10
90
20
10
0.01
1
0.2
0.001
0.6
50
NOTES
1
Typicals represent average readings at +25°C.
2
V
REFH
can be any value between GND and V
DD
, for the AD8804 V
REFL
can be any value between GND and V
DD
.
3
Guaranteed by design and not subject to production test.
4
Digital Input voltages V
IN
= 0 V or V
DD
for CMOS condition. DAC outputs unloaded. P
DISS
is calculated from (I
DD
×
V
DD
).
5
Measured at a V
OUT
pin where an adjacent V
OUT
pin is making a full-scale voltage change (f = 100 kHz).
6
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
–2–
REV. 0
AD8802/AD8804
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C, unless otherwise noted)
PIN CONFIGURATIONS
V
REFH
1
O1 2
O2 3
O3 4
O4 5
O5 6
20 V
DD
19
RS
18 O12
17 O11
V
REFH
1
O1 2
O2 3
O3 4
O4 5
O5 6
20 V
DD
19 O12
18 O11
17 O10
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V
V
REFX
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (T
J
MAX – T
A
)/θ
JA
Thermal Resistance
θ
JA,
SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
AD8802 PIN DESCRIPTIONS
AD8802
16 O10
AD8804
16 O9
TOP VIEW 15 O9
(Not to Scale)
14 O8
O6 7
SHDN
8
CS
9
GND 10
13 O7
12 SDI
11 CLK
TOP VIEW 15
O8
(Not to Scale)
14 O7
O6 7
SHDN
8
CS
9
GND 10
13 SDI
12 CLK
11 V
REFL
AD8804 PIN DESCRIPTIONS
Pin Name
1
2
3
4
5
6
7
8
9
V
REF
O1
O2
O3
O4
O5
O6
SHDN
CS
Description
Common DAC Reference Input
DAC Output #1, addr = 0000
2
DAC Output #2, addr = 0001
2
DAC Output #3, addr = 0010
2
DAC Output #4, addr = 0011
2
DAC Output #5, addr = 0100
2
DAC Output #6, addr = 0101
2
Reference input current goes to zero. DAC
latch settings maintained
Chip Select Input, Active Low. When
CS
returns high, data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register
Ground
Serial Clock Input, Positive Edge Triggered
Serial Data Input
DAC Output #7, addr = 0110
2
DAC Output #8, addr = 0111
2
DAC Output #9, addr = 1000
2
DAC Output #10, addr = 1001
2
DAC Output #11, addr = 1010
2
DAC Output #12, addr = 1011
2
Asynchronous Preset to Midscale Output
Setting. Loads all DAC Registers with 80
H
Positive Power Supply, Specified for Operation
at Both +3 V and +5 V
Pin Name
1
2
3
4
5
6
7
8
9
V
REFH
O1
O2
O3
O4
O5
O6
SHDN
CS
Description
Common High-Side DAC Reference Input
DAC Output #1, addr = 0000
2
DAC Output #2, addr = 0001
2
DAC Output #3, addr = 0010
2
DAC Output #4, addr = 0011
2
DAC Output #5, addr = 0100
2
DAC Output #6, addr = 0101
2
Reference input current goes to zero DAC latch
settings maintained
Chip Select Input, Active Low. When
CS
returns
high, data in the serial input register is decoded
based on the address bits and loaded input the
target DAC register
Ground
Common Low-Side DAC Reference Input
Serial Clock Input, Positive Edge Triggered
Serial Data Input
DAC Output #7, addr = 0110
2
DAC Output #8, addr = 0111
2
DAC Output #9, addr = 1000
2
DAC Output #10, addr = 1001
2
DAC Output #11, addr = 1010
2
DAC Output #12, addr = 1011
2
Positive power supply, specified for operation at
both +3 V and +5 V
ORDERING GUIDE
Temperature
Range
– 40°C/+85°C
– 40°C/+85°C
– 40°C/+85°C
– 40°C/+85°C
– 40°C/+85°C
– 40°C/+85°C
Package
Description
PDIP-20
SOL-20
TSSOP-20
PDIP-20
SOL-20
TSSOP-20
Package
Option
N-20
R-20
RU-20
N-20
R-20
RU-20
10
11
12
13
14
15
16
17
18
19
20
GND
CLK
SDI
O7
O8
O9
O10
O11
O12
RS
V
DD
10
11
12
13
14
15
16
17
18
19
20
GND
V
REFL
CLK
SDI
O7
O8
O9
O10
O11
O12
V
DD
Model
AD8802AN
AD8802AR
AD8802ARU
AD8804AN
AD8804AR
AD8804ARU
FTN
RS
RS
RS
REFL
REFL
REFL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8802/AD8804–Typical Performance Characteristics
1
0.75
0.5
0.25
INL – LSB
0
–0.25
–0.5
–0.75
–1
0
32
64
96
128
160
CODE – Decimal
192
224
256
I
REF
CURRENT – µA
V
DD
= +5V
V
REFH
= +5V
V
REFL
= 0V
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
160
140
120
100
80
60
40
20
0
0
32
64
96
128
160
CODE – Decimal
192
224
256
V
DD
= +5V
V
REFH
= +2V
V
REFL
= 0V
ONE DAC CHANGING WITH CODE,
OTHER DACs SET TO 00H
T
A
= +25°C
Figure 1. INL vs. Code
Figure 4. Input Reference Current vs. Code
1
0.75
0.5
0.25
INL – LSB
10k
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
SHUTDOWN CURRENT – nA
V
DD
= +5V
V
REFH
= +5V
V
REFL
= 0V
1k
V
DD
= +5.5V
V
REF
= +5.5V
100
0
–0.25
–0.5
–0.75
–1
0
32
64
96
128
160
CODE – Decimal
192
224
256
10
V
DD
= +2.7V
V
REF
= +2.7V
0
–55
–35
–15
5
25
45
65
TEMPERATURE –
°C
85
105
125
Figure 2. Differential Nonlinearity Error vs. Code
Figure 5. Shutdown Current vs. Temperature
1600
V
DD
= +4.5V
V
REF
= +4.5V
1280
V
REFL
= 0V
SS = 3600 PCS
FREQUENCY
100k
10k
1k
100
10
1
0.1
0.01
V
DD
= +5.5V
V
IN
= +5.5V
V
DD
= +5.5V
V
IN
= +2.4V
960
640
320
0
0
0.2
0.4
0.6
0.8
1.0
ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB
SUPPLY CURRENT – µA
T
A
= +25°C
0.001
–55
–35
–15
5
25
45
65
TEMPERATURE –
°C
85
105
125
Figure 3. Total Unadjusted Error Histogram
Figure 6. Supply Current vs. Temperature
–4–
REV. 0
MCU
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