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Quad, 12-Bit, 50/65 MSPS,
Serial, LVDS, 3 V A/D Converter
AD9229
FEATURES
Four ADCs in 1 package
Serial LVDS digital output data rates
to 780 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 69.5 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
400 MHz full power analog bandwidth
Power dissipation
1,350 mW at 65 MSPS
985 mW at 50 MSPS
1 V p-p to 2 V p-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
FUNCTIONAL BLOCK DIAGRAM
PDWN
DTP
DRVDD
DRGND
AD9229
VIN+A
VIN–A
VIN+B
VIN–B
VIN+C
VIN–C
VIN+D
VIN–D
SHA
SHA
SHA
SHA
PIPELINE
ADC
12
SERIAL
LVDS
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
PIPELINE
ADC
12
SERIAL
LVDS
PIPELINE
ADC
12
SERIAL
LVDS
PIPELINE
ADC
12
SERIAL
LVDS
VREF
SENSE
0.5V
REFT
REFB
REF
SELECT
DATA RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
04418-001
APPLICATIONS
Digital beam-forming systems for ultrasound
Wireless and wired broadband communications
Communication test equipment
AGND
LVDSBIAS
CLK
Figure 1.
GENERAL DESCRIPTION
The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance in applications
where a small package size is critical.
The ADC requires a single 3 V power supply and TTL-/CMOS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported and typically consumes 3 mW when enabled.
Fabricated with an advanced CMOS process, the AD9229 is
available in a Pb-free, 48-lead LFCSP package. It is specified
over the industrial temperature range of –40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Four ADCs are contained in a small, space-saving package.
A data clock out (DCO) is provided, which operates up to
390 MHz and supports double-data rate operation (DDR).
The outputs of each ADC are serialized LVDS with data
rates up to 780 Mbps (12 bits × 65 MSPS).
The AD9229 operates from a single 3.0 V power supply.
Packaged in a Pb-free, 48-lead LFCSP package.
The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9229
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagram ............................................................................... 7
Absolute Maximum Ratings............................................................ 8
Explanation of Test Levels ........................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Equivalent Circuits ......................................................................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
Analog Input Considerations ................................................... 18
Clock Input Considerations...................................................... 19
Evaluation Board ............................................................................ 24
Power Supplies ............................................................................ 24
Input Signals................................................................................ 24
Output Signals ............................................................................ 24
Default Operation and Jumper Selection Settings................. 25
Alternate Analog Input Drive Configuration......................... 25
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 39
REVISION HISTORY
9/05—Rev. 0 to Rev. A
Change to Specifications.................................................................. 3
Changes to Differential Input Configurations Section.............. 19
Changes to Exposed Paddle Thermal Heat Slug
Recommendations Section........................................................ 23
Changes to Evaluation Board Section.......................................... 24
Changes to Table 11........................................................................ 36
3/05—Revision 0: Initial Version
Rev. A | Page 2 of 40
AD9229
SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 1.
AD9229-50
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
1
Gain Matching
1
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
1
Reference Voltage, VREF = 1 V
REFERENCE
Output Voltage Error, VREF = 1 V
Load Regulation @ 1.0 mA, VREF = 1 V
Output Voltage Error, VREF = 0.5 V
Load Regulation @ 0.5 mA,
VREF = 0.5 V
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range
VREF = 1 V
Differential Input Voltage Range
VREF = 0.5 V
Common Mode Voltage
Input Capacitance
2
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
DRVDD
Power Dissipation
3
Power-Down Dissipation
CROSSTALK
4
1
2
AD9229-65
Max
Min
12
Typ
Max
Unit
Bits
Temperature
Test
Level
Min
12
Typ
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
V
VI
V
VI
V
V
V
VI
V
VI
V
V
VI
VI
V
V
V
IV
IV
VI
VI
VI
V
V
2.7
2.7
Guaranteed
±5
±5
±0.3
±0.2
±0.3
±0.3
±0.6
±0.6
±2
±12
±16
±10
3
±8
0.2
7
2
1
1.5
7
400
3.0
3.0
300
28
985
3
–95
±25
±25
±2.5
±1.5
±0.6
±1
Guaranteed
±5
±5
±0.3
±0.2
±0.3
±0.3
±0.4
±0.4
±3
±12
±16
±25
±25
±2.5
±1.5
±0.7
±1
mV
mV
% FS
% FS
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±30
±17
±10
3
±8
0.2
7
2
1
1.5
7
400
±30
±17
mV
mV
mV
mV
kΩ
V p-p
V p-p
V
pF
MHz
3.6
3.6
330
31
1083
2.7
2.7
3.0
3.0
420
29
1350
3
–95
3.6
3.6
455
33
1465
V
V
mA
mA
mW
mW
dB
Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3
Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS.
4
Typical specification over the first Nyquist zone.
Rev. A | Page 3 of 40
AD9229
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
AD9229-50
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
Temperature
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
25°C
25°C
Test
Level
IV
V
VI
VI
V
V
V
VI
VI
V
V
V
VI
VI
V
V
V
VI
VI
V
V
V
VI
VI
V
V
V
VI
VI
V
V
Min
69.5
68.7
Typ
70.4
70.4
69.6
67.2
70.0
70.0
69.4
67.3
66.8
11.3
11.3
11.2
10.9
10.8
85
85
85
73
78
–85
–85
–85
–78
–90
–90
–88
–85
–73
Max
Min
69.0
AD9229-65
Typ
70.2
70.2
69.5
67.1
69.8
69.8
69.0
66.7
11.3
11.3
11.2
10.8
85
85
85
77
–85
–85
–85
–77
–90
–90
–81.7
–88
–83
–73
–79.7
–73
Max
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
SIGNAL-TO-NOISE RATIO (SINAD)
EFFECTIVE NUMBER OF BITS
(ENOB)
f
IN
= 2.4 MHz
f
IN
= 10.3 MHz
f
IN
= 25 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 2.4 MHz
f
IN
= 10.3 MHz
f
IN
= 25 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 2.4 MHz
f
IN
= 10.3 MHz
f
IN
= 25 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 2.4 MHz
f
IN
= 10.3 MHz
f
IN
= 25 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 2.4 MHz
f
IN
= 10.3 MHz
f
IN
= 25 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 2.4 MHz
f
IN
= 10.3 MHz
f
IN
= 25 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN1
= 15 MHz
f
IN2
= 16 MHz
f
IN1
= 69 MHz
f
IN2
= 70 MHz
68.0
68.4
11.1
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
76
WORST HARMONIC
(Second or Third)
–76
WORST OTHER
(Excluding Second or Third)
TWO-TONE INTERMODULATION
DISTORTION (IMD)
AIN1 and AIN2 = –7.0 dBFS
25°C
V
–68.5
–68.5
dBc
Rev. A | Page 4 of 40
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