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ISL6219A
Data Sheet
March 20, 2007
FN9093.1
Microprocessor CORE Voltage Regulator
Precision Multi-Phase BUCK PWM
Controller for Mobile Applications
The ISL6219A provides core-voltage regulation by driving up
to three interleaved synchronous-rectified buck-converter
channels in parallel. Intersil multi-phase controllers together
with ISL6207 gate drivers form the basis for the most reliable
power-supply solutions available to power the latest
industry-leading microprocessors. Multi-phase buck-converter
architecture uses interleaved timing to multiply ripple
frequency and reduce input and output ripple currents. Lower
ripple results in lower total component cost, reduced
dissipation, and smaller implementation area. Pre-configured
for 3-phase operation, the ISL6219A offers the flexibility of
2-phase operation. Simply connect the unused PWM pin to
+5V. The channel switching frequency is adjustable in the
range of 100kHz to 1.5MHz giving the designer the ultimate
flexibility in managing the balance between high-speed
response and good thermal management.
New features on the ISL6219A include Dynamic-VID™
technology allowing seamless on-the-fly VID changes with
no need for any additional external components. When the
ISL6219A receives a new VID code, it incrementally steps
the output voltage to the new level. Dynamic VID™ changes
are fast and reliable with no output voltage overshoot or
undershoot.
Like other Intersil multiphase controllers, the ISL6219A uses
cost and space-saving r
DS(ON)
sensing for channel current
balance and dynamic voltage positioning. Channel current
balancing is automatic and accurate with the integrated
current-balance control system. Overcurrent protection can be
tailored to any application with no need of additional parts.
An integrated DAC decodes the 5-bit logic signal present at
VID0-VID4 and provides an accurate reference for precision
voltage regulation. The high-bandwidth error amplifier and
accurate voltage reference all work together to provide
better than 0.8% total system accuracy, and to enable the
fastest transient response available. A window comparator
toggles PGOOD if the output voltage moves out of range
and acts to protect the load in case of overvoltage.
Features
• Multi-Phase Power Conversion
• Active Channel Current Balancing
• Lossless current sense scheme
- Uses MOSFET’s r
DS(ON)
- Optional current sense method for higher precision
• Precision CORE Voltage Regulation
-
±0.8%
System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- Dynamic VID technology
- 5-Bit VID Input
- 1.100V to 1.850V in 25mV Steps
• Programmable Droop Voltage
• Fast Transient Recovery Time
• Overvoltage, Undervoltage and Overcurrent Protection
• Power-Good Output
• 2 or 3 Phase Operation
• User selectable Switching Frequency of 100kHz to 1.5MHz
- 200kHz - 4.5MHz Effective Ripple Frequency
ISL6219A
(28 LD QSOP)
TOP VIEW
VID 0 1
VID 1 2
VID 2 3
VID 3 4
VID 4 5
NC 6
FS/EN 7
NC 8
FB 9
COMP 10
NC 11
NC 12
NC 13
GND 14
28 VCC
27 NC
26 NC
25 PGOOD
24 NC
23 ISEN1
22 PWM1
21 PWM2
20 ISEN2
19 ISEN3
18 PWM3
17 NC
16 VSEN
15 NC
Ordering Information
PART NUMBER
ISL6219ACA*
ISL6219ACAZ* (Note)
PART MARKING
ISL 6219ACA
ISL6219 ACAZ
TEMP. RANGE (°C)
-10 to +85
-10 to +85
PACKAGE
28 Ld QSOP
28 Ld QSOP (Pb-free)
PKG. DWG. #
M28.15
M28.15
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Dynamic VID is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6219A
Block Diagram
PGOOD
VCC
POWER-ON
RESET (POR)
VSEN
X 0.83
+
UV
-
OV
LATCH
THREE-STATE
CLOCK AND
SAWTOOTH
GENERATOR
+
∑
-
+
PWM
-
FS/EN
+
OV
X1.15
-
PWM1
SOFT-
START
AND FAULT
LOGIC
+
∑
-
+
PWM
-
PWM2
COMP
+
∑
-
+
PWM
-
PWM3
VID0
VID1
VID2
VID3
VID4
DYNAMIC
VID
D/A
+
E/A
-
FB
CURRENT
CORRECTION
PHASE
NUMBER
CHANNEL
DETECTOR
ISEN1
I_TOT
-
OC
+
I_TRIP
+
+
∑
+
ISEN3
ISEN2
GND
2
FN9093.1
March 20, 2007
ISL6219A
Typical Application - 3-Phase Buck Converter
+5V
VIN
VCC
EN
BOOT
UGATE
PHASE
L
1
ISL6207
R
FB
R
C
PWM1
+5V
DRIVER
LGATE
GND
C
C
FB
COMP
VCC
+5V
VIN
VSEN
VCC
EN
R
ISEN1
PWM2
PWM1
PWM2
R
ISEN2
ISEN2
PWM3
FS/EN
RT
EN
ISEN3
+5V
VIN
BOOT
UGATE
PHASE
L
2
PGOOD
VID0
VID1
VID2
VID3
VID4
ISL6219A
ISEN1
ISL6207
DRIVER
LGATE
GND
R
ISEN3
µP
LOAD
VCC
BOOT
UGATE
PHASE
L
3
GND
ISL6207
PWM3
DRIVER
LGATE
GND
C
O
3
FN9093.1
March 20, 2007
ISL6219A
Functional Pin Descriptions
VID0, VID1, VID2, VID3, VID4 (Pins 1, 2, 3, 4, 5)
These are the inputs to the internal DAC that provide the
reference voltage for output regulation. Each pin has an
internal 20μA pull-up current source to 2.5V making the parts
compatible with CMOS and TTL logic from 5V down to 2.5V.
When a VID change is detected the reference voltage slowly
ramps up or down to the new value in 25mV steps. Connect
these pins to either open-drain or active-pull-up type outputs.
Pulling these pins above 2.9V can cause a reference offset
inaccuracy.
GND (Pin 14)
Bias and signal ground for the IC.
VSEN (Pin 15)
Power good monitor input. Connect to the microprocessor
CORE voltage.
PWM3, PWM2, PWM1 (Pins 18, 21, 22)
Pulse-width modulation outputs. These logic outputs tell the
driver IC(s) when to turn the MOSFETs on and off.
ISEN3, ISEN2, ISEN1 (PINS 19, 20, 23)
Current sense inputs. A resistor connected between these
pins and the respective phase nodes has a current
proportional to the current in the lower MOSFET during its
conduction interval. The current is used as a reference for
channel balancing, load sharing, protection, and load-line
regulation.
FS/EN (Pin 7)
This is a dual function pin. A resistor placed from FS/EN to
ground sets the switching frequency. There is an inverse
relationship between the value of the resistor and the
switching frequency. This pin can also be used to disable the
controller. To disable the controller, pull this pin below 1V.
FB (Pin 8) and COMP (Pin 9)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to an external R-C
network to compensate the regulator.
PGOOD (Pin 25)
Power good. This pin is an open-drain logic signal that
indicates when the microprocessor CORE voltage (VSEN
pin) is within specified limits and soft-start has timed out.
VCC (Pin 28)
Bias supply voltage for the controller. Connect this pin to a
5V power supply.
4
FN9093.1
March 20, 2007
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