K7N801801M
Document Title
512Kx18-Bit Pipelined NtRAM
TM
512Kx18 Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Changed DC parameters
I
CC
; from 450mA to 420mA at 150MHZ.
I
SB1
; from 10mA to 20mA, I
SB2
; from 10mA to 20mA.
1. Changed t
CD
from 4.0ns to 4.2ns at -75
2. Changed DC condition at Icc and parameters
I
SB1
; from 20mA to 30mA,
I
SB2
; from 20mA to 30mA.
1. A
DD
119BGA(7x17 Ball Grid Array Package) .
2. A
DD
x32 organization.
1.Changed V
OL
Max value from 0.2V to 0.4V at 2.5V I/O.
1. Final Spec Release.
2. Remove x32 organization.
1. Remove V
DDQ
Supply voltage( 2.5V I/O )
1. Changed t
OE
from 4.2ns to 3.8ns at -75 , from 5.0ns to 3.8ns at -10
1. Add V
DDQ
Supply voltage( 2.5V I/O )
Draft Date
June. 09. 1998
Aug. 19. 1998
Remark
Preliminary
Preliminary
0.2
Sep. 09. 1998
Preliminary
0.3
Oct. 15. 1998
Preliminary
0.4
1.0
Dec. 23 .1998
Jan. 29. 1999
Preliminary
Final
2.0
3.0
4.0
Feb. 25. 1999
Mar. 22. 1999
May. 13. 1999
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
May 1999
Rev 4.0
K7N801801M
512Kx18-Bit Pipelined NtRAM
TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention only for TQFP.
•
Α
interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
•100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).
512Kx18 Pipelined NtRAM
TM
GENERAL DESCRIPTION
The K7N801801M is 9,437,184 bits Synchronous Static
SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N801801M is implemented with SAMSUNG′s high per-
formance CMOS technology and is available in 100pin TQFP
and 119BGA packages. Multiple power and ground pins mini-
mize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -15 -13 -10 Unit
t
CYC
t
CD
t
OE
6.7 7.5
10
ns
ns
ns
3.8 4.2 5.0
3.8 3.8 3.8
LOGIC BLOCK DIAGRAM
LBO
A [0:18]
ADDRESS
REGISTER
A
2
~A
18
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
512Kx18
MEMORY
ARRAY
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x= a,b)
OE
ZZ
18
DQa
0
~ DQb
8
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung,
and its architecture and functionalities are supported by NEC and Toshiba.
-2-
May 1999
Rev 4.0
K7N801801M
PIN CONFIGURATION
(TOP VIEW)
BWb
BWa
512Kx18 Pipelined NtRAM
TM
CKE
ADV
CS
2
N.C.
N.C.
N.C.
CLK
CS
1
CS
2
V
DD
V
SS
WE
A
18
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
85
88
89
87
98
97
92
93,94
86
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
8,9,12,13,18,19,22,23,24
58,59,62,63,68,69,72,73,
74
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
LBO
V
SS
DQa
0
~a
8
DQb
0
~b
8
Data Inputs/Outputs
V
DDQ
V
SSQ
Output Power Supply
(3.3V or 2.5V)
Output Ground
Notes :
1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-3-
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
8
DQb
7
V
SSQ
V
DDQ
DQb
6
DQb
5
V
DD
V
DD
V
DD
V
SS
DQb
4
DQb
3
V
DDQ
V
SSQ
DQb
2
DQb
1
DQb
0
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N801801M(512Kx18)
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQa
0
DQa
1
DQa
2
V
SSQ
V
DDQ
DQa
3
DQa
4
V
SS
V
DD
V
DD
ZZ
DQa
5
DQa
6
V
DDQ
V
SSQ
DQa
7
DQa
8
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
May 1999
Rev 4.0
K7N801801M
119BGA PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
K7N801801M(512Kx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
NC
V
DDQ
2
A
CS
2
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQPb
A
A
NC
3
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
LBO
A
NC
4
NC
CKE
V
DD
NC
CS
1
OE
ADV
NC
V
DD
CLK
NC
WE
A
1
*
A
0
*
V
DD
NC
NC
512Kx18 Pipelined NtRAM
TM
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
NC
A
NC
6
A
A
A
DQPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
Note :
*A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN NAME
SYMBOL
A
A
0
,A
1
ADV
WE
CLK
CKE
CS
1
CS
2
BWx
(x=a,b)
OE
ZZ
LBO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Byte Write Inputs
PIN NAME
V
DD
V
SS
N.C.
SYMBOL
Power Supply
Ground
No Connect
PIN NAME
DQa
DQb
DQPa, Pb
V
DDQ
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Power Supply
Output Enable
Power Sleep Mode
Burst Mode Control
-4-
May 1999
Rev 4.0
K7N801801M
FUNCTION DESCRIPTION
512Kx18 Pipelined NtRAM
TM
The K7N801801M is NtRAM
TM
designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAM
TM
latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS
1
, CS
2
, CS
2
)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS
1
, CS
2
, CS
2
) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[b:a] can be used for byte write operation. The pipe-
lined NtRAM
TM
uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
(Interleaved Burst, LBO=High)
Case 4
A
0
0
1
0
1
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
BQ TABLE
LBO PIN
LOW
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
(Linear Burst, LBO=Low)
Case 4
A
0
0
1
0
1
A
1
1
0
0
1
A
0
1
0
1
0
Fourth Address
Note :
1. LBO pin must be tied to High or Low, and Floating State must not be allowed
.
-5-
May 1999
Rev 4.0
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