K7P163666A-HC300 datasheet, PDF

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K7P163666A-HC300: DescriptionStandard SRAM, 512KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, BGA-119; Categorystorage storage; File Size320KB，14 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7P163666A-HC300 Overview

Standard SRAM, 512KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, BGA-119

K7P163666A-HC300 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	1.6 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	18874368 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.2 mm
Maximum supply voltage (Vsup)	2.63 V
Minimum supply voltage (Vsup)	2.37 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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K7P163666A

K7P161866A

Document Title

512Kx36 & 1Mx18 Synchronous Pipelined SRAM

512Kx36 & 1Mx18 SRAM

Revision History

Rev. No.

Rev. 0.0

Rev. 0.1

History

- Initial Document

- Absolute maximum ratings are changed

: 2.815 - > 3.13

DDQ

: 2.815 - > 2.4

TERM

: 2.815 - > VDDQ+0.5 (2.4V MAX)

- Recommended DC operating conditions are changed

REF

/ V

-CLK : 0.68 - > 0.6, 0.95 - > 0.9

- DC characteristics is changed

SBZZ

: 150 - > 128

- AC Characteristics are changed

AVKH

/ T

DVKH

/ T

WVKH

/ T

SVKH

: 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3

KHAX

/ T

KHDX

/ T

KHWX

/ T

KHSX

: 0.5 / 0.5 / 0.5 - > 0.5 / 0.6 / 0.6

Draft Date

Dec. 2001

Oct. 2002

Remark

Advance

Rev. 0.2

- Recommended DC operating condition is changed

Max V

DIF-CLK

: V

DDQ

+0.3 -> V

DDQ

+0.6

- Correct typo

DD ->

DDQ

: in MODE CONTROL at page4

Jan. 2003

Advance

Rev. 0.3

Sep. 2003

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

-1-

Sep. 2003

Rev 0.3

K7P163666A

K7P161866A

FUNCTION DESCRIPTION

512Kx36 & 1Mx18 SRAM

The K7P163666A and K7P161866A are 18,874,368 bit Synchronous Pipeline Mode SRAM. It is organized as 524,288 words of 36

bits(or 1,048,576 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology.

Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the

updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one

cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second

edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this

cycle, signaling that the SRAM should drive out the data.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write (Stire) Operation

All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,

one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the

Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.

Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write

cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of

read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the

same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be

done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is

the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the

SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have

new byte data from the write data buffer and the other bytes from the SRAM array.

Programmable Impedance Output Buffer Operation

This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance

can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM

and V

. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250

Ω

resistor will give an output buffer impedance of 50

Ω

. The allowable range of RQ is from 175

Ω

to 350

Ω

. Internal circuits evaluate and

periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-

ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the

optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.

Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance

match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum

number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-

tion by connecting ZQ to V

or V

Mode Control

There are two mode control select pins (M

and M

) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M

must be connected to V

and M

must be connected to V

DDQ

. These

mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.

Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

-4-

Sep. 2003

Rev 0.3

K7P163666A

K7P161866A

FUNCTION DESCRIPTION

512Kx36 & 1Mx18 SRAM

The K7P163666A and K7P161866A are 18,874,368 bit Dual Mode (supports both Register Register and Late Select Mode) SRAM

devices. They are organized as 524,288 words by 36 bits for K7P163666A and 1,048,576 words by 18 bits for K7P161866A, fabri-

cated using Samsung's advanced CMOS technology. Late Write/Pipelined Read(RR) for x36/x18 organizations and Late Write/Late

Select Read(LS) for x36 organization are supported.

The chip is operated with a single +2.5V power supply and is compatible wtih HSTL input and output. The package is 119(7x17)

Plastic Ball Grid Array with balls on a 1.27mm pitch.

Read Operation for Register Register Mode(x36 and x18)

During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is

read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock.

Read Operation for Late Select Mode(x36)

During read operations, addresses(SA) and controls except the Way Select Address(SAS) are registered during the first rising edge

of K clock. The internal array(x72 bit data) is read between the first edge and the second edge, and as the Way Select Address(SAS)

is registered at the second clock edge, x36 bit data is mux selected before the output register.

Write Operation(Late Write)

During write operations, addresses including the Way Select Address(SAS) and controls are registered at the first rising edge of K

clock and data inputs are registered at the following rising edge of K clock. Write addresses and data inputs are stored in the data in

registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array. Byte write

operation is supported using SW[a:d] and the timing of SW[a:d] is the same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be

done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is

the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored

write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the

SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have

new byte data from the write data buffer and the other bytes from the SRAM array.

Programmable Impedance Output Buffer Operation

This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance

can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM

and V

. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250

Ω

resistor will give an output buffer impedance of 50

Ω

. The allowable range of RQ is from 175

Ω

to 350

Ω

. Internal circuits evaluate and

periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-

ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the

optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.

Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance

match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum

number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-

tion by connecting ZQ to V

or V

Mode Control

There are two mode control select pins (M

and M

) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M

must be connected to V

and M

must be connected to V

. These

mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.

Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

-5-

Sep. 2003

Rev 0.3

K7P163666A-HC300 Related Products

	K7P163666A-HC300	K7P163666A-HC330	K7P163666A-HC30T	K7P161866A-HC330	K7P161866A-HC300	K7P161866A-HC250	K7P163666A-HC250
Description	Standard SRAM, 512KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 512KX36, 1.5ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 512KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 1MX18, 1.5ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 1MX18, 1.6ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 1MX18, 2ns, CMOS, PBGA119, 14 X 22 MM, BGA-119	Standard SRAM, 512KX36, 2ns, CMOS, PBGA119, 14 X 22 MM, BGA-119
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,	BGA,
Contacts	119	119	119	119	119	119	119
Reach Compliance Code	unknown	compliant	unknown	unknown	compliant	unknown	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	1.6 ns	1.5 ns	1.6 ns	1.5 ns	1.6 ns	2 ns	2 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
length	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	36	36	36	18	18	18	36
Number of functions	1	1	1	1	1	1	1
Number of terminals	119	119	119	119	119	119	119
word count	524288 words	524288 words	524288 words	1048576 words	1048576 words	1048576 words	524288 words
character code	512000	512000	512000	1000000	1000000	1000000	512000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	512KX36	512KX36	512KX36	1MX18	1MX18	1MX18	512KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.2 mm	2.2 mm	2.2 mm	2.2 mm	2.2 mm	2.2 mm	2.2 mm
Maximum supply voltage (Vsup)	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V	2.63 V
Minimum supply voltage (Vsup)	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V	2.37 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm

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