531WB235M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531WB235M000DGR

531WB235M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 235MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531WB235M000DGR Overview

CMOS/TTL Output Clock Oscillator, 235MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531WB235M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknow
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	235 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

MAX630 minimum structure DC-DC conversion circuit diagram

Measurement of voltage, current and power of general frequency converter main circuit

Gree FBI-40B1 computer-type remote control wall fan receiver circuit diagram

Continuously adjustable positive and negative voltage stabilized power supply circuit

Variable LC Oscillator Circuit

Computer motherboard circuit diagram 810 1_30

Grab EE New Year's Lucky Bag - Share my New Year here: Spending Chinese New Year in the countryside, the last time going to the market... Does it have the flavor of Chinese New Year? Does it bring back any memories?...; ketose Talking

Filter function judgment: Determine what function the signal output in the figure implements (high pass, low pass, band pass, etc.) Uo1 is low pass, Uo2 is band pass, Uo3 is band pass; how do you tell? It's a bit hard to tell...; 1nnocent Analog electronics

Solar powered circular aircraft: [img]http://www.diytd.com/uploadfile/20070410140756724.jpg[/img] The "Solar Circular Plane" I designed and made uses solar energy as its energy source to simulate an airplane flying around the earth i...; yuandayuan6999 Energy Infrastructure?

I would like to ask how to store the data received by the STM32 DMA serial port into an array and then send it out through the serial port. Thank you.: int main(void) {SysTick_Config(SystemCoreClock/1000);LCD_Port_Init(115200);while(1){if(RxOverFlag2 = 1){USART_SendString2(USART_RXBUF);USART_SendString3(buzzer);}} }/*函数名称：DMA_Configuration2函数用途：STM32...; 小子不乖1229 Embedded System

Can anyone recommend some good tutorials?: rt...; 瓜妞妞 Embedded System

I recently made a PCB and used PADS to simulate it, but the actual board didn't look good.: I recently made a PCB and used PADS to simulate it. The actual board effect is not good. I will find a more accurate simulator....; kata PCB Design

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components