552EK1134M000DG datasheet, PDF

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552EK1134M000DG: DescriptionOscillator; CategoryPassive components oscillator; File Size237KB，14 Pages; ManufacturerSilicon Laboratories Inc

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552EK1134M000DG Overview

Oscillator

552EK1134M000DG Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown

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Si 5 5 2

EVISION

U A L

R E Q U E N C Y

O L TA G E

- C

O N T R O L L E D

R Y S TA L

S C I L L A T O R

( V C X O ) 1 0 MH

Z T O

1.4 G H

Features

Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz

Two selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH

xDSL

10 GbE LAN/WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Ordering Information:

See page 8.

Description

The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low-jitter clocks in noisy environments typically found in communication

systems. The Si552 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Pin Assignments:

See page 7.

(Top View)

GND

CLK–

CLK+

Functional Block Diagram

CLK- CLK+

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 0.6 6/07

Si552

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