ZPSD412A1-70LI datasheet, PDF - EEWORLD Datasheet

ZPSD412A1-70LI: Description64KX8 UVPROM, 40 I/O, PIA-GENERAL PURPOSE, CQCC68, WINDOWED, CERAMIC, LDCC-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，108 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ZPSD412A1-70LI Overview

64KX8 UVPROM, 40 I/O, PIA-GENERAL PURPOSE, CQCC68, WINDOWED, CERAMIC, LDCC-68

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	QFN
package instruction	WINDOWED, CERAMIC, LDCC-68
Contacts	68
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	7e-8 ns
Other features	GENERAL PURPOSE ZPLD
JESD-30 code	S-GQCC-J68
JESD-609 code	e0
length	24.13 mm
Number of I/O lines	40
Number of ports	5
Number of terminals	68
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	WQCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER, WINDOW
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
ROM size (bits)	512 Bits
Maximum seat height	4.57 mm
Maximum standby current	0.00002 A
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
UV erasable	Y
width	24.13 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

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