DM7450N datasheet, PDF - EEWORLD Datasheet

DM7450N: DescriptionExpandable Dual 2-Wide 2-Input AND-OR-INVERT Gate; Categorylogic logic; File Size80KB，4 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM7450N Overview

Expandable Dual 2-Wide 2-Input AND-OR-INVERT Gate

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	National Semiconductor（TI ）
package instruction	DIP, DIP14,.3
Reach Compliance Code	unknow
Other features	2 EXPAND INPUTS FOR 1 FUNCTION
series	TTL/H/L
JESD-30 code	R-PDIP-T14
JESD-609 code	e0
length	19.18 mm
Load capacitance (CL)	15 pF
Logic integrated circuit type	AND-OR-INVERT GATE
MaximumI(ol)	0.016 A
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	14 mA
Prop。Delay @ Nom-Su	30 ns
propagation delay (tpd)	15 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

	DM7450N	DM7450
Description	Expandable Dual 2-Wide 2-Input AND-OR-INVERT Gate	Expandable Dual 2-Wide 2-Input AND-OR-INVERT Gate

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