Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (TSSOP only; soldering, 10s) ............+300°C
Soldering Temperature (reflow) .......................................+260°C
RECOMMENDED OPERATING CONDITIONS
(T
A
= -40°C to +95°C, unless otherwise noted.)
PARAMETER
Supply Voltage
Input Logic 1 (SDA, SCL)
Input Logic 0 (SDA, SCL)
Resistor Inputs (L0, L1, H0, H1)
Resistor Current
High-Impedance Resistor
Current
Input Logic Levels (IN1, IN2)
I
RES
I
ROFF
Input logic 1
Input logic 0
2
0.8
SYMBOL
V
CC
V
IH
V
IL
(Note 1)
(Note 2)
(Note 2)
CONDITIONS
MIN
2.85
0.7 x V
CC
-0.3
-0.3
-3
0.001
TYP
MAX
5.50
V
CC
+ 0.3
+0.3 x V
CC
V
CC
+ 0.3
+3
0.1
UNITS
V
V
V
V
mA
μA
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
Supply Current
Input Leakage
Low-Level Output Voltage
(SDA, OUT1, OUT2)
Full-Scale Input (MON1, MON2,
MON3)
Full-Scale V
CC
Monitor
I/O Capacitance
Digital Power-On Reset
Analog Power-On Reset
C
I/O
POD
POA
POD < POA (Note 7)
1.0
1.875
SYMBOL
I
CC
I
IL
V
OL1
3mA sink current
At factory setting
(Note 5)
At factory setting (Note 6)
(Note 4)
-200
0
2.4875
6.5208
2.5
6.5536
CONDITIONS
MIN
TYP
1
MAX
2
+200
0.4
2.5125
6.5864
10
2.5
2.65
UNITS
mA
nA
V
V
V
pF
V
V
2
Maxim Integrated
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
ANALOG RESISTOR CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
Position 00h Resistance (50k )
Position FFh Resistance (50k )
INL
DNL
Temperature Coefficient
T
A
= +25°C
T
A
= +25°C
(Note 8)
(Note 9)
(Note 10)
CONDITIONS
MIN
0.72
40
-2
-1
±50
TYP
0.9
50
MAX
1.08
60
+2
+1
UNITS
k
k
LSB
LSB
ppm/°C
ANALOG VOLTAGE MONITORING
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
ADC Resolution
INL
DNL
Input Resolution
Supply Resolution
Input/Supply Accuracy
(MON1, MON2, MON3, V
CC
)
Update Rate for MON1, MON2,
MON3, Temp, or V
CC
Input/Supply Offset
(MON1, MON2, MON3, V
CC
)
Factory Setting Full Scale
Temperature LSB Weighting
VMON
V
CC
A
CC
t
FRAME
V
OS
(Note 6)
MON1, MON2, MON3 (Note 5)
V
CC
(Note 5)
At factory setting
T
A
= +25°C
-3
-1
610
1.6
0.25
32
0
2.5
6.5536
1/256
0.5
40
1
SYMBOL
CONDITIONS
MIN
TYP
13
+3
+1
MAX
UNITS
Bits
LSB
LSB
μV
mV
% FS
(full scale)
ms
LSB
V
°C
DIGITAL THERMOMETER
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
Thermometer Error
SYMBOL
T
ERR
CONDITIONS
-40°C to +95°C
MIN
TYP
MAX
±3.0
UNITS
°C
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, unless otherwise noted.) (Note 3)
PARAMETER
EEPROM Writes
SYMBOL
CONDITIONS
+70°C (Note 7)
MIN
50,000
TYP
MAX
UNITS
Writes
Maxim Integrated
3
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted. See Figure 5.) (Note 3)
PARAMETER
SCL Clock Frequency
Bus Free Time Between STOP
and START Condition
Hold Time (Repeated)
START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Data Hold Time
Data Setup Time
START Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Setup Time for STOP Condition
Capacitive Load for Each Bus
EEPROM Write Time
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
HD:DAT
t
SU:DAT
t
SU:STA
t
R
t
F
t
SU:STO
C
B
t
W
(Note 14)
10
(Note 14)
(Note 14)
(Notes 12, 13)
(Note 11)
CONDITIONS
MIN
0
1.3
0.6
1.3
0.6
0
100
0.6
20 + 0.1C
B
20 + 0.1C
B
0.6
400
20
300
300
0.9
TYP
MAX
400
UNITS
kHz
μs
μs
μs
μs
μs
ns
μs
ns
ns
μs
pF
ms
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +95°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
SDA and SCL are connected to V
CC
and all other input signals are connected to well-defined logic levels.
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the
voltage on the inputs is greater than full scale.
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V
CC
voltage.
Guaranteed by design.
INL is the difference of measured value from expected value at DAC position. The expected value is a straight line from
measured minimum position to measured maximum position.
DNL is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope
of the straight line from measured minimum position to measured maximum position.
See the
Typical Operating Characteristics.
After this period, the first clock pulse is generated.
The maximum t
HD:DAT
only has to be met if the device does not stretch the low period (t
LOW
) of the SCL signal.
A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
IH_MIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
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