tive data under multiple layers of advanced physical
security to provide the most secure key storage possible.
The DeepCover Secure Authenticator (DS2465) is a
SHA-256 coprocessor with built-in 1-Wire
®
master that
provides the SHA-256 and memory functionality required
by a host system to communicate with and operate a
1-Wire SHA-256 slave. In addition, it performs protocol
conversion between the I
2
C master and any attached
1-Wire SHA-256 slaves. For 1-Wire line driving, internal
user-adjustable timers relieve the system host processor
from generating time-critical 1-Wire waveforms, support-
ing both standard and overdrive 1-Wire communication
speeds. The 1-Wire line can be powered down under
software control. Strong pullup features support 1-Wire
power delivery to 1-Wire devices such as EEPROMs.
When not in use, the DS2465 can be put in sleep mode
where power consumption is minimal.
Ordering Information
appears at end of data sheet.
Features
S
SHA-256 Engine to Operate a Symmetric-Key-
Based Bidirectional Secure Authentication Model
S
Two 32-Byte Pages of User EEPROM with Multiple
Programmable Protection Options
S
1-Wire Master Port with Selectable Active or
Passive 1-Wire Pullup
S
Strong 1-Wire Pullup Provided by an Internal Low-
Impedance Signal Path
S
1-Wire Port Can Be Powered Down Under
Software Control
S
I
2
C Operating (Pullup) Voltage: 3.3V ±10%
S
Operating Range: 3.3V ±10%, -40NC to +85NC
S
6-Pin TSOC Package
Applications
Authentication of Consumables
Secure Feature Control
Typical Application Circuit
3V
R
P
(I
2
C PORT)
µC
SLPZ
SDA
SCL
V
CC
R
P
= 1.1kΩ
MAXIMUM I
2
C BUS CAPACITANCE 320pF
DS2465
1-Wire LINE
IO
DS28E15
#1
DS28E15
#2
DS28E15
#n
DeepCover is a trademark and 1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
219-0017; Rev 2; 1/13
ABRIDGED DATA SHEET
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to GND ........-0.5V to +4.0V
Maximum Current into Any Pin...........................................20mA
Operating Temperature Range ......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) .....................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
Supply Current
Power-On Reset Trip Point
1-Wire Input High
1-Wire Input Low
1-Wire Weak Pullup Resistor
(Notes 3, 4)
1-Wire Output Low
Active Pullup On Threshold
Active Pullup On Time
(Notes 3, 5)
Active Pullup Impedance
1-Wire Output Fall Time (Note 3)
IO PIN: 1-Wire TIMING (Note 6)
Reset Low Time
Reset High Time
Presence-Detect Sample Time
Sampling for Short and Interrupt
t
RSTL
t
RSTH
t
MSP
t
SI
Standard
Overdrive
Standard and overdrive
Standard
Overdrive
Standard
Overdrive
Standard
Write-1/Read Low Time
t
W1L
Overdrive
-5%
7.6
1.9
7.6
-5%
-5%
See
Table 6
+9%
Fs
Fs
Fs
Fs
SYMBOL
V
CC
I
CC
V
POR
V
IH1
V
IL1
R
WPU
V
OL1
V
IAPO
t
APU
R
APU
t
F
Low range
High range
V
CC
= 2.97V, 8mA sink current
(Note 3)
1-Wire time slot
1-Wire reset standard speed
1-Wire reset overdrive speed
V
CC
= 2.97V, 4mA load (Note 3)
Standard
Overdrive
0.25
0.05
0.95
375
750
500
1000
(Note 2)
Sleep mode (SLPZ pin low), V
CC
= 3.63V
(Note 3)
0.6
O
V
CC
0.2
O
V
CC
750
1350
0.25
1.2
V
Fs
I
Fs
Equal to t
REC0
2.375
2.5
2.625
0.475
0.5
0.525
60
1
0.2
0.5
1.0
CONDITIONS
MIN
2.97
TYP
3.3
MAX
3.63
750
1.0
1.4
UNITS
V
FA
V
V
V
I
Equal to t
RSTL
See
Table 6
8
2
8
See
Table 6
+9%
8.72
2.18
8.72
+9%
Fs
Maxim Integrated
2
ABRIDGED DATA SHEET
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Read Sample Time
Write-0 Low Time
Write-0 Recovery Time
1-Wire Time Slot
SHA-256 ENGINE
Computation Current
Computation Time
EEPROM
Programming Current
Programming Time for a 32-Bit
Segment
Write/Erase Cycling Endurance
Data Retention
SLPZ PIN
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Wake-Up Time from Sleep Mode
I
2
C SCL AND SDA PINS (Note 13)
Low Level Input Voltage
High Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs
Low Level Output Voltage at 3mA
Sink Current
Output Fall Time from V
IH(MIN)
to
V
IL(MAX)
with a Bus Capacitance
from 10pF to 400pF
Pulse Width of Spikes That Are
Suppressed by the Input Filter
Input Current with an Input
Voltage Between 0.1V
CC(MAX)
and 0.9V
CC(MAX)
V
IL
V
IH
V
HYS
V
OL
t
OF
t
SP
I
I
(Note 3)
60
(Note 3)
-0.5
0.7
O
V
CC
0.05
O
V
CC
0.4
0.3
O
V
CC
V
CC(MAX)
+ 0.5V
V
V
V
V
V
IL
V
IH
I
I
t
SWUP
Pin at 3.63V (Note 3)
(Note 12)
-0.5
0.7
O
V
CC
0.3
O
V
CC
V
CC
+
0.5V
0.1
200
V
V
FA
Fs
I
PROG
t
PROG
N
CY
t
DR
T
A
= +85NC (Notes 8, 9)
T
A
= +85NC (Notes 10, 11)
100k
10
(Notes 3, 7)
2
10
mA
ms
—
Years
I
CSHA
t
CSHA
Refer to the full data sheet.
mA
ms
SYMBOL
t
MSR
t
W0L
t
REC0
t
slot
Standard
Overdrive
Standard
Overdrive
Standard and overdrive
Standard and overdrive
CONDITIONS
MIN
11.4
1.4
-5%
-5%
TYP
12
1.5
See
Table 6
See
Table 6
MAX
13.1
1.64
+9%
+9%
UNITS
Fs
Fs
Fs
Fs
Equal to t
W0L
+ t
REC0
250
ns
(Note 3)
50
ns
(Notes 3, 14)
-10
+10
FA
Maxim Integrated
3
ABRIDGED DATA SHEET
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition; After this Period, the
First Clock Pulse is Generated
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus Line
Oscillator Warmup Time
SYMBOL
C
I
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
t
OSCWUP
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Notes 3, 15, 16)
(Notes 3, 17)
(Note 3)
(Note 3)
(Notes 3, 18)
(Note 12)
250
0.6
1.3
400
200
(Note 3)
0
0.6
1.3
0.6
0.6
0.9
CONDITIONS
MIN
TYP
MAX
10
400
UNITS
pF
kHz
Fs
Fs
Fs
Fs
Fs
ns
Fs
Fs
pF
Fs
Note 1:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2:
Operating current with 1-Wire write byte sequence followed by continuous read of 1-Wire Master Status register at 400kHz
in overdrive.
Note 3:
Guaranteed by design and/or characterization only. Not production tested.
Note 4:
Active pullup or resistive pullup and range are configurable.
Note 5:
The active pullup does not apply to the rising edge of a presence pulse outside of a 1-Wire Reset Pulse command or
during the recovery after a short on the 1-Wire line.
Note 6:
All 1-Wire timing specifications are derived from the same timing circuit.
Note 7:
Current drawn from V
CC
during the EEPROM programming interval or SHA-256 computation.
Note 8:
Write-cycle endurance is tested in compliance with JESD47G.
Note 9:
Not 100% production tested; guaranteed by reliability monitor sampling.
Note 10:
Data retention is tested in compliance with JESD47G.
Note 11:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 12:
I
2
C communication should not take place for the max t
OSCWUP
or t
SWUP
time following a power-on reset or a wake-up
from sleep mode.
Note 13:
All I
2
C timing values are referred to V
IH(MIN)
and V
IL(MAX)
levels.
Note 14:
I/O pins of the DS2465 do not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 15:
The DS2465 provides a hold time of at least 300ns for the SDA signal (referenced to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 16:
The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the setup time before it releases the clock (I
2
C bus specification
Rev. 03, 19 June 2007).
Note 17:
A fast-mode I
2
C bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU:DAT
R
250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+ t
SU:DAT
= 1000 +
250 = 1250ns (according to the standard-mode I
2
C bus specification) before the SCL line is released. Also the acknowl-
edge timing must meet this setup time (I
2
C bus specification Rev. 03, 19 June 2007).
Note 18:
C
B
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable may vary from this value depend-
ing on the actual operating voltage and frequency of the application (I
2
C bus specification Rev. 03, 19 June 2007).
Maxim Integrated
4
ABRIDGED DATA SHEET
DS2465
DeepCover Secure Authenticator with
SHA-256 Coprocessor and 1-Wire Master Function
Pin Configuration
TOP VIEW
+
GND
IO
V
CC
1
2
3
DS2465
6 SCL
5
4
SDA
SLPZ
Detailed Description
The DS2465 is a SHA-256 coprocessor with built-in
1-Wire master and two pages of user memory.
Refer to the full data sheet for this information.
TSOC
Pin Description
PIN
1
2
3
NAME
GND
IO
V
CC
FUNCTION
Ground Reference
I/O Driver for 1-Wire Line
Power-Supply Input
Active-Low Control Input. Activates the
low-power sleep mode and issues a
device reset of the SHA-coprocessor and
the 1-Wire master (equivalent to the
1-Wire Master Reset command).
I
2
C Serial-Data Input/Output. Must be
connected to V
CC
through a pullup
resistor.
I
2
C Serial-Clock Input. Must be connect-
ed to V
CC
through a pullup resistor.
4
SLPZ
5
SDA
The self-timed 1-Wire master function supports advanced
1-Wire waveform features including standard and over-
drive speeds, active pullup, and strong pullup for power
delivery. The active pullup affects rising edges on the
1-Wire side. The strong pullup function uses the same
pullup transistor as the active pullup, but with a differ-
ent control algorithm. Once supplied with command
and data, the input/output controller of the DS2465 per-
forms time-critical 1-Wire communication functions such
as reset/presence-detect cycle, read-byte, write-byte,
single-bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, and search direction taken) through
the 1-Wire Master Status register and data through the
1-Wire Read Data register. All registers, the user memory
and a scratchpad are located in a linear address space
for direct access. The DS2465 communicates with a host
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