W632GG8KB
32M
8 BANKS
8 BIT DDR3 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
GENERAL DESCRIPTION ................................................................................................................... 5
FEATURES ........................................................................................................................................... 5
ORDER INFORMATION ....................................................................................................................... 6
KEY PARAMETERS ............................................................................................................................. 7
BALL CONFIGURATION ...................................................................................................................... 8
BALL DESCRIPTION ............................................................................................................................ 9
BLOCK DIAGRAM .............................................................................................................................. 11
FUNCTIONAL DESCRIPTION ............................................................................................................ 12
Basic Functionality .............................................................................................................................. 12
RESET and Initialization Procedure .................................................................................................... 12
8.2.1
8.2.2
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.1.3
8.3.1.4
8.3.1.5
8.3.1.6
8.3.2
8.3.2.1
8.3.2.2
8.3.2.3
8.3.2.4
8.3.2.5
8.3.2.6
8.3.2.7
8.3.3
8.3.3.1
8.3.3.2
8.3.3.3
8.3.3.4
8.3.4
8.3.4.1
8.4
8.5
8.6
Power-up Initialization Sequence ..................................................................................... 12
Reset Initialization with Stable Power .............................................................................. 14
Mode Register MR0 ......................................................................................................... 17
Burst Length, Type and Order ................................................................................ 17
CAS Latency........................................................................................................... 18
Test Mode............................................................................................................... 18
DLL Reset............................................................................................................... 18
Write Recovery ....................................................................................................... 19
Precharge PD DLL ................................................................................................. 19
Mode Register MR1 ......................................................................................................... 19
DLL Enable/Disable ................................................................................................ 20
Output Driver Impedance Control ........................................................................... 20
ODT RTT Values .................................................................................................... 20
Additive Latency (AL) ............................................................................................. 20
Write leveling .......................................................................................................... 20
Output Disable ........................................................................................................ 21
TDQS, TDQS#........................................................................................................ 21
Mode Register MR2 ......................................................................................................... 22
Partial Array Self Refresh (PASR) .......................................................................... 23
CAS Write Latency (CWL) ...................................................................................... 23
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) ............................. 23
Dynamic ODT (Rtt_WR) ......................................................................................... 23
Mode Register MR3 ......................................................................................................... 24
Multi Purpose Register (MPR) ................................................................................ 24
Programming the Mode Registers....................................................................................................... 15
No OPeration (NOP) Command .......................................................................................................... 25
Deselect Command ............................................................................................................................. 25
DLL-off Mode ...................................................................................................................................... 25
Publication Release Date: Dec. 24, 2013
Revision A02
-1-
W632GG8KB
8.7
DLL on/off switching procedure ........................................................................................................... 26
8.7.1
8.7.2
8.8
8.8.1
8.8.2
8.9
8.9.1
8.9.2
8.9.3
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.11
8.12
8.13
DLL “on” to DLL “off” Procedure ....................................................................................... 26
DLL “off” to DLL “on” Procedure ....................................................................................... 27
Frequency change during Self-Refresh............................................................................ 28
Frequency change during Precharge Power-down .......................................................... 28
DRAM setting for write leveling & DRAM termination function in that mode .................... 31
Write Leveling Procedure ................................................................................................. 31
Write Leveling Mode Exit ................................................................................................. 33
MPR Functional Description ............................................................................................. 35
MPR Register Address Definition ..................................................................................... 36
Relevant Timing Parameters ............................................................................................ 36
Protocol Example ............................................................................................................. 36
Input clock frequency change.............................................................................................................. 28
Write Leveling ..................................................................................................................................... 30
Multi Purpose Register ........................................................................................................................ 34
ACTIVE Command.............................................................................................................................. 42
PRECHARGE Command .................................................................................................................... 42
READ Operation ................................................................................................................................. 43
8.13.1
8.13.2
8.13.2.1
8.13.2.2
8.13.2.3
8.13.2.4
8.13.2.5
8.13.2.6
READ Burst Operation ..................................................................................................... 43
READ Timing Definitions .................................................................................................. 44
READ Timing; Clock to Data Strobe relationship.................................................... 45
READ Timing; Data Strobe to Data relationship ..................................................... 46
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................. 47
tRPRE Calculation .................................................................................................. 48
tRPST Calculation .................................................................................................. 48
Burst Read Operation followed by a Precharge...................................................... 54
DDR3 Burst Operation ..................................................................................................... 56
WRITE Timing Violations ................................................................................................. 56
Motivation ............................................................................................................... 56
Data Setup and Hold Violations .............................................................................. 56
Strobe to Strobe and Strobe to Clock Violations..................................................... 56
Write Timing Parameters ........................................................................................ 56
Write Data Mask............................................................................................................... 57
tWPRE Calculation........................................................................................................... 58
tWPST Calculation ........................................................................................................... 58
8.14
WRITE Operation ................................................................................................................................ 56
8.14.1
8.14.2
8.14.2.1
8.14.2.2
8.14.2.3
8.14.2.4
8.14.3
8.14.4
8.14.5
8.15
8.16
8.17
Refresh Command .............................................................................................................................. 65
Self-Refresh Operation ....................................................................................................................... 67
Power-Down Modes ............................................................................................................................ 69
8.17.1
8.17.2
8.17.3
Power-Down Entry and Exit ............................................................................................. 69
Power-Down clarifications - Case 1 ................................................................................. 75
Power-Down clarifications - Case 2 ................................................................................. 75
Publication Release Date: Dec. 24, 2013
Revision A02
-2-
W632GG8KB
8.17.4
8.18
8.18.1
8.18.2
8.18.3
8.19
8.19.1
8.19.2
8.19.2.1
8.19.2.2
8.19.2.3
8.19.3
8.19.3.1
8.19.3.2
8.19.4
8.19.4.1
8.19.4.2
8.19.4.3
8.19.4.4
low periods
9.
9.1
9.2
9.3
10.
10.1
10.2
10.3
10.4
10.5
10.6
Power-Down clarifications - Case 3 ................................................................................. 76
ZQ Calibration Description ............................................................................................... 77
ZQ Calibration Timing ...................................................................................................... 78
ZQ External Resistor Value, Tolerance, and Capacitive loading ...................................... 78
ODT Mode Register and ODT Truth Table ...................................................................... 79
Synchronous ODT Mode .................................................................................................. 80
ODT Latency and Posted ODT ............................................................................... 80
Timing Parameters ................................................................................................. 80
ODT during Reads .................................................................................................. 82
Dynamic ODT .................................................................................................................. 83
Functional Description: ........................................................................................... 83
ODT Timing Diagrams ............................................................................................ 84
Asynchronous ODT Mode ................................................................................................ 88
Synchronous to Asynchronous ODT Mode Transitions .......................................... 89
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry .. 89
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit..... 92
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
93
ZQ Calibration Commands .................................................................................................................. 77
On-Die Termination (ODT) .................................................................................................................. 79
OPERATION MODE ........................................................................................................................... 94
Command Truth Table ........................................................................................................................ 94
CKE Truth Table ................................................................................................................................. 96
Simplified State Diagram ..................................................................................................................... 97
ELECTRICAL CHARACTERISTICS ................................................................................................... 98
Absolute Maximum Ratings................................................................................................................. 98
Operating Temperature Condition ....................................................................................................... 98
DC & AC Operating Conditions ........................................................................................................... 99
10.3.1
Recommended DC Operating Conditions ........................................................................ 99
Input and Output Leakage Currents .................................................................................................... 99
Interface Test Conditions .................................................................................................................... 99
DC and AC Input Measurement Levels ............................................................................................. 100
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
10.7
10.7.1
10.7.1.1
10.7.1.2
DC and AC Input Levels for Single-Ended Command and Address Signals .................. 100
DC and AC Input Levels for Single-Ended Data Signals ................................................ 101
Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ........... 103
Single-ended requirements for differential signals ......................................................... 104
Differential Input Cross Point Voltage ............................................................................ 105
Slew Rate Definitions for Single-Ended Input Signals .................................................... 106
Slew Rate Definitions for Differential Input Signals ........................................................ 106
Output Slew Rate Definition and Requirements ............................................................. 107
Single Ended Output Slew Rate ........................................................................... 108
Differential Output Slew Rate ............................................................................... 109
DC and AC Output Measurement Levels .......................................................................................... 107
Publication Release Date: Dec. 24, 2013
Revision A02
-3-
W632GG8KB
10.8
10.9
34 ohm Output Driver DC Electrical Characteristics .......................................................................... 110
10.8.1
10.9.1
10.9.2
10.9.3
10.9.4
10.10
10.10.1
10.10.2
10.11
10.12
10.12.1
10.12.2
10.13
10.13.1
10.13.2
10.14
10.15
10.15.1
10.15.2
10.15.3
10.15.4
10.16
10.16.1
10.16.2
10.16.3
10.16.4
10.16.5
11.
12.
Output Driver Temperature and Voltage sensitivity ........................................................ 112
ODT Levels and I-V Characteristics ............................................................................... 113
ODT DC Electrical Characteristics ................................................................................. 114
ODT Temperature and Voltage sensitivity ..................................................................... 114
Design guide lines for RTT
PU
and RTT
PD
....................................................................... 115
ODT Timing Definitions............................................................................................................ 116
Test Load for ODT Timings ............................................................................................ 116
ODT Timing Definitions .................................................................................................. 116
Input/Output Capacitance ........................................................................................................ 120
Overshoot and Undershoot Specifications............................................................................... 121
AC Overshoot /Undershoot Specification for Address and Control Pins: ....................... 121
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins: ......... 121
IDD and IDDQ Specification Parameters and Test Conditions ................................................ 122
IDD and IDDQ Measurement Conditions ....................................................................... 122
IDD Current Specifications ............................................................................................. 132
Clock Specification .................................................................................................................. 133
Speed Bins .............................................................................................................................. 134
DDR3-1333 Speed Bin and Operating Conditions ......................................................... 134
DDR3-1600 Speed Bin and Operating Conditions ......................................................... 135
DDR3-1866 Speed Bin and Operating Conditions ......................................................... 136
Speed Bin General Notes .............................................................................................. 137
AC Characteristics ................................................................................................................... 138
AC Timing and Operating Condition for -11 speed grade .............................................. 138
AC Timing and Operating Condition for -12/12I/12A/12K/-15/15I/15A/15K speed grades
142
Timing Parameter Notes ................................................................................................ 146
Address / Command Setup, Hold and Derating ............................................................. 149
Data Setup, Hold and Slew Rate Derating ..................................................................... 156
On-Die Termination (ODT) Levels and Characteristics ..................................................................... 113
PACKAGE SPECIFICATION ............................................................................................................ 158
REVISION HISTORY ........................................................................................................................ 159
Publication Release Date: Dec. 24, 2013
Revision A02
-4-
W632GG8KB
1. GENERAL DESCRIPTION
The W632GG8KB is a 2G bits DDR3 SDRAM, organized as 33,554,432 words
8 banks
8 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for general
applications. W632GG8KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -15, 15I,
15A and 15K. The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12,
12I, 12A and 12K speed grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I
industrial grade which is guaranteed to support -40°C ≤ T
CASE
≤ 95°C). The -15, 15I, 15A and 15K
speed grades are compliant to the DDR3-1333 (9-9-9) specification (the 15I industrial grade which is
guaranteed to support -40°C ≤ T
CASE
≤ 95°C).
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (T
A
) surrounding the device cannot be less than -40°C or greater than +95°C (for 12A
and 15A), +105°C (for 12K and 15K), and the case temperature (T
CASE
) cannot be less than -40°C or
greater than +95°C (for 12A and 15A), +105°C (for 12K and 15K). JEDEC specifications require the
refresh rate to double when T
CASE
exceeds +85°C; this also requires use of the high-temperature self
refresh option. Additionally, ODT resistance and the input/output impedance must be derated when
T
CASE
is < 0°C or > +85°C.
The W632GG8KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: V
DD
, V
DDQ
= 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Publication Release Date: Dec. 24, 2013
Revision A02
-5-
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