1517
5-TAP DIP DELAY LINE
T
D
/T
R
= 3
(SERIES 1517)
FEATURES
•
•
•
•
•
•
5 taps of equal delay increment
Delays as large as 300ns available
Low DC resistance
Standard 14-pin DIP package
Epoxy encapsulated
Meets or exceeds MIL-D-23859C
IN
N/C
T2
N/C
T4
T5
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
N/C
T1
N/C
T3
N/C
N/C
N/C
data
3
®
delay
devices,
inc.
PACKAGES
1517-xxz
xx = Delay (T
D
)
z = Impedance Code
FUNCTIONAL DESCRIPTION
The 1517-series device is a fixed, single-input, five-output, passive delay
line. The signal input (IN) is reproduced at the outputs (T1-T5) in equal
increments. The delay from IN to T5 (T
D
) is given by the device dash
number. The characteristic impedance of the line is given by the letter
code that follows the dash number (See Table). The rise time (T
R
) of the
line is 33% of T
D
, and the 3dB bandwidth is given by 1.05 / T
D
.
PIN DESCRIPTIONS
IN
Signal Input
T1-T5 Tap Outputs
GND Ground
SERIES SPECIFICATIONS
•
•
•
•
•
Dielectric breakdown:
Distortion @ output:
Operating temperature:
Storage temperature:
Temperature coefficient:
50 Vdc
10% max.
-55°C to +125°C
-55°C to +125°C
100 PPM/°C
FUNCTIONAL DIAGRAM
T1 T2 T3 T4
IN
GND
T5
DASH NUMBER SPECIFICATIONS
Part
Number
1517-10A
1517-15A
1517-20A
1517-30A
1517-40A
1517-5B
1517-10B
1517-15B
1517-20B
1517-25B
1517-30B
1517-40B
1517-50B
1517-60B
1517-75B
1517-10C
1517-20C
1517-30C
1517-40C
1517-50C
1517-60C
Delay
(ns)
10.0
±
1.0
15.0
±
1.0
20.0
±
1.0
30.0
±
1.5
40.0
±
2.0
5.0
±
1.0
10.0
±
1.0
15.0
±
1.0
20.0
±
1.0
25.0
±
1.3
30.0
±
1.5
40.0
±
2.0
50.0
±
2.5
60.0
±
3.0
75.0
±
3.8
10.0
±
1.0
20.0
±
1.0
30.0
±
1.5
40.0
±
2.0
50.0
±
2.5
60.0
±
3.0
Imped
(Ω)
Ω
50
50
50
50
50
100
100
100
100
100
100
100
100
100
100
200
200
200
200
200
200
RDC
(Ω)
Ω
0.6
0.6
0.7
0.7
0.9
0.5
0.7
0.7
0.9
1.0
1.5
1.8
2.0
2.0
2.5
1.5
2.0
2.5
3.0
3.0
3.5
Part
Number
1517-80C
1517-90C
1517-120C
1517-150C
1517-25D
1517-37D
1517-50D
1517-60D
1517-75D
1517-100D
1517-150D
1517-15E
1517-30E
1517-50E
1517-60E
1517-75E
1517-90E
1517-120E
1517-130E
1517-180E
1517-220E
Delay
(ns)
80.0
±
4.0
90.0
±
4.5
120.0
±
6.0
150.0
±
7.5
25.0
±
1.3
37.0
±
1.9
50.0
±
2.5
60.0
±
3.0
75.0
±
3.8
100.0
±
5.0
150.0
±
7.5
15.0
±
1.0
30.0
±
1.5
50.0
±
2.5
60.0
±
3.0
75.0
±
3.8
90.0
±
4.5
120.0
±
6.0
130.0
±
6.5
180.0
±
9.0
220.0
±
11.0
Imped
(Ω)
Ω
200
200
200
200
250
250
250
250
250
250
250
300
300
300
300
300
300
300
300
300
300
RDC
(Ω)
Ω
3.5
5.0
5.0
8.0
2.5
3.0
3.5
4.0
4.0
5.0
8.5
2.5
3.0
4.0
4.0
4.5
5.5
8.0
9.0
11.0
13.0
Part
Number
1517-20F
1517-40F
1517-60F
1517-80F
1517-100F
1517-120F
1517-160F
1517-180F
1517-240F
1517-300F
1517-25G
1517-50G
1517-75G
1517-100G
1517-125G
1517-150G
1517-200G
1517-225G
1517-300G
Delay
(ns)
20.0
±
1.0
40.0
±
2.0
60.0
±
3.0
80.0
±
4.0
100.0
±
5.0
120.0
±
6.0
160.0
±
8.0
180.0
±
9.0
240.0
±
12.0
300.0
±
15.0
25.0
±
1.3
50.0
±
2.5
75.0
±
3.8
100.0
±
5.0
125.0
±
6.3
150.0
±
7.5
200.0
±
10.0
225.0
±
11.3
300.0
±
15.0
Imped
(Ω)
Ω
400
400
400
400
400
400
400
400
400
400
500
500
500
500
500
500
500
500
500
RDC
(Ω)
Ω
4.5
5.0
5.0
8.0
9.0
10.0
13.0
14.0
19.0
23.0
3.0
5.0
8.0
15.0
9.0
13.0
21.0
23.0
29.0
©
2001 Data Delay Devices
Doc #01007
10/30/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1517
14 13 12 11 10
9
8
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
1
2
3
4
5
6
7
.780 MAX.
.280
MAX.
See
Table
.015 TYP.
.010±.002
.018
TYP.
.070 MAX.
.600±.010
6 Equal spaces
each .100±.010
Non-Accumulative
.350
MAX.
Package Dimensions
PASSIVE DELAY LINE TEST SPECIFICATIONS
TEST CONDITIONS
INPUT:
Ambient Temperature:
Input Pulse:
Source Impedance:
Rise/Fall Time:
Pulse Width
Period
Pulse Width
Period
(T
D
<= 75ns):
(T
D
<= 75ns):
(T
D
> 75ns):
(T
D
> 75ns):
25 C
±
3 C
High = 3.0V typical
Low = 0.0V typical
50Ω Max.
3.0 ns Max. (measured
at 10% and 90% levels)
PW
IN
= 100ns
PER
IN
= 1000ns
PW
IN
= 2 x T
D
PER
IN
= 10 x T
D
o
o
OUTPUT:
R
load
:
C
load
:
Threshold:
10MΩ
10pf
50% (Rising & Falling)
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
PER
IN
PW
IN
T
RISE
INPUT
SIGNAL
90%
50%
10%
T
FALL
V
IH
90%
50%
10%
V
IL
D
FALL
D
RISE
T
RISE
OUTPUT
SIGNAL
90%
50%
10%
T
FALL
V
OH
90%
50%
10%
V
OL
Timing Diagram For Testing
OUT
PULSE
GENERATOR
TRIG
R
IN
IN
DEVICE UNDER
TEST (DUT)
50
Ω
T1
T2
T3
T4
T5
IN
TRIG
OSCILLOSCOP
R
IN
= R
OUT
= Z
LINE
R
OUT
Test Setup
Doc #01007
10/30/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com
2
京公网安备 11010802033920号
EEWORLD
