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SY100E151JITR

Description
6-BIT D REGISTER
Categorylogic    logic   
File Size61KB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric Compare View All

SY100E151JITR Overview

6-BIT D REGISTER

SY100E151JITR Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicrochip
Parts packaging codeQLCC
package instructionQCCJ,
Contacts28
Reach Compliance Codecompli
series100E
JESD-30 codeS-PQCC-J28
JESD-609 codee0
length11.48 mm
Logic integrated circuit typeD FLIP-FLOP
Humidity sensitivity level1
Number of digits6
Number of functions1
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)240
propagation delay (tpd)0.8 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
surface mountYES
technologyECL
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width11.48 mm
minfmax1100 MHz
6-BIT D
REGISTER
SY10E151
SY100E151
FINAL
FEATURES
s
1100MHz toggle frequency
s
Extended 100E V
EE
range of –4.2V to –5.46V
s
s
s
s
Differential outputs
Asynchronous Master Reset
Dual clocks
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E151
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E151 offer 6 edge-triggered, high-speed,
master-slave D-type flip-flops with differential outputs,
designed for use in new, high-performance ECL systems.
The two external clock signals (CLK
1
, CLK
2
) are gated
through a logical OR operation before use as clocking
control for the flip-flops. Data is clocked into the flip-flops
on the rising edge of either CLK
1
or CLK
2
(or both). When
both CLK
1
and CLK
2
are at a logic LOW, data enters the
master and is transferred to the slave when either CLK
1
or
CLK
2
(or both) go HIGH.
The MR (Master Reset) signal operates asynchronously
to make all Q outputs go to a logic LOW.
BLOCK DIAGRAM
D
0
Q
0
R
D
1
D
R
D
2
D
R
D
3
D
R
D
4
D
R
D
5
D
R
CLK
1
CLK
2
M
R
Q
0
PIN CONFIGURATION
MR
CLK
2
CLK
1
NC
V
CCO
Q
5
Q
5
18
17
D
25 24 23 22 21 20 19
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
D
5
D
4
D
3
V
EE
D
2
D
1
D
0
26
27
28
1
2
3
4
5
6
7
8
9
10 11
Q
4
Q
4
V
CC
Q
3
Q
3
Q
2
Q
2
PLCC
TOP VIEW
J28-1
16
15
14
13
12
V
CCO
Q
0
Q
1
Q
1
Q
4
Q
4
Q
5
Q
5
PIN NAMES
Pin
D
0
–D
5
CLK
1
, CLK
2
MR
Q
0
–Q
5
Q
0
–Q
5
V
CCO
Function
Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverting Outputs
V
CC
to Output
V
CCO
Rev.: E
NC
Q
0
Amendment: /0
1
Issue Date: November 2002

SY100E151JITR Related Products

SY100E151JITR SY100E151JI SY10E151JC SY10E151JCTR
Description 6-BIT D REGISTER 6-BIT D REGISTER 6-BIT D REGISTER 6-BIT D REGISTER
Maker Microchip Microchip Microchip -
package instruction QCCJ, PLASTIC, LCC-28 LCC-28 -
Reach Compliance Code compli compli compli -
series 100E 100E 10E -
JESD-30 code S-PQCC-J28 S-PQCC-J28 S-PQCC-J28 -
length 11.48 mm 11.48 mm 11.48 mm -
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP -
Number of digits 6 6 6 -
Number of functions 1 1 1 -
Number of terminals 28 28 28 -
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code QCCJ QCCJ QCCJ -
Package shape SQUARE SQUARE SQUARE -
Package form CHIP CARRIER CHIP CARRIER CHIP CARRIER -
propagation delay (tpd) 0.8 ns 0.8 ns 0.8 ns -
Maximum seat height 4.57 mm 4.57 mm 4.57 mm -
surface mount YES YES YES -
technology ECL ECL ECL -
Terminal form J BEND J BEND J BEND -
Terminal pitch 1.27 mm 1.27 mm 1.27 mm -
Terminal location QUAD QUAD QUAD -
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE -
width 11.48 mm 11.48 mm 11.48 mm -
minfmax 1100 MHz 1100 MHz 1100 MHz -
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