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SY100101422-7FCS

Description
256 x 4 ECL RAM
File Size233KB,10 Pages
ManufacturerETC
Download Datasheet View All

SY100101422-7FCS Overview

256 x 4 ECL RAM

SEMICONDUCTOR
SYNERGY
256 x 4 ECL RAM
SY100422-3/4/5/7
SY101422-3/4/5/7
SY10422-3/4/5/7
SY100422-3/4/5/7
SY10422-3/4/5/7
SY101422-3/4/5/7
FEATURES
s
Address access time, t
AA
: 3/4/5/7ns max.
s
Block select access time, t
AB
: 2ns max.
s
Write pulse width, t
WW
: 3ns min.
s
Edge rate, tr/tf: 500ps typ.
s
Write recovery times under 5ns
s
Power supply current, I
EE
: –250mA, –200mA
for –5/7ns
s
Superior immunity against alpha particles provides
virtually no soft error sensitivity
s
Built with advanced ASSET™ technology
s
Fully compatible with industry standard 10K/100K
ECL I/O levels
s
Noise margins improved with on-chip voltage and
temperature compensation
s
Open emitter output for easy memory expansion
s
Includes popular Block Select function allowing
individual read/write control over blocks
s
ESD protection of 2000V
s
Available in 24-pin flatpack and 28-pin PLCC and
MLCC packages
DESCRIPTION
The Synergy SY10/100/101422 are 1024-bit Random
Access Memories (RAMs), designed with advanced Emitter
Coupled Logic (ECL) circuitry. The devices are organized
as 256-words-by-4-bits and meet the standard 10K/100K
family signal levels. The SY100422 is also supply voltage-
compatible with 100K ECL, while the SY101422 operates
from 10K ECL supply voltage (–5.2V). All feature on-chip
voltage and temperature compensation for improved noise
margin.
The SY10/100/101422 employ proprietary circuit design
techniques and Synergy’s proprietary ASSET advanced
bipolar technology to achieve extremely fast access, write
pulse width and write recovery times. ASSET uses
proprietary technology concepts to achieve significant
reduction in parasitic capacitance while improving device
packing density. Synergy’s circuit design techniques, coupled
with ASSET, result not only in ultra-fast performance, but
also allow device operation at reduced power levels with
virtually no soft error sensitivity and with outstanding device
reliability in volume production.
BLOCK DIAGRAM
A
0
A
5
A
6
A
7
Y-Decoder/Driver
A
2
A
3
A
4
X-Decoder/
Driver
A
1
Memory Cell Array
WE
SA/WA*
SA/WA
SA/WA
SA/WA
DI
0
BS
0
DO
0
*
SA = Sense Amplifier
WA = Write Amplifier
DI
1
BS
1
DO
1
DI
2
BS
2
DO
2
DI
3
BS
3
DO
3
© 1999 Micrel-Synergy
Rev.: E
Amendment: /0
1
Issue Date: August,1999
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