EMC646SP16KZ-12LF datasheet, PDF

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EMC646SP16KZ-12LF: Description4Mx16 bit CellularRAM AD-MUX; File Size505KB，52 Pages; ManufacturerEMLSI; Websitehttp://www.emlsi.com

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EMC646SP16KZ-12LF Overview

4Mx16 bit CellularRAM AD-MUX

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Preliminary

EMC646SP16K

4Mx16 CellularRAM AD-MUX

Document Title

4Mx16 bit CellularRAM AD-MUX

Revision History

Revision No.

0.0

History

Initial Draft

Draft Date

July 13,2007

Remark

Preliminary

Emerging Memory & Logic Solutions Inc.

4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea

Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com

Zip Code : 690-717

The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to

your questions about device. If you have any questions, please contact the EMLSI office.

Preliminary

EMC646SP16K

4Mx16 CellularRAM AD-MUX

Table of Contents

Features..............................................................................................................................................................................................

Options...........................................................................................................................................................................................

General Description............................................................................................................................................................................

Functional Description........................................................................................................................................................................

Power-Up Initialization....................................................................................................................................................................

Bus Operating Modes.........................................................................................................................................................................

Asynchronous Mode.......................................................................................................................................................................

Burst Mode Operation....................................................................................................................................................................

Mixed-Mode Operation ..................................................................................................................................................................

WAIT Operation .............................................................................................................................................................................

LB# / UB# Operation......................................................................................................................................................................

Low-Power Operation......... ...............................................................................................................................................................

Standby Mode Operation ...............................................................................................................................................................

Temperature Compensated Refresh..............................................................................................................................................

Partial Array Refresh .....................................................................................................................................................................

Registers.............................................................................................................................................................................................

Access Using CRE ........................................................................................................................................................................

Software Access ............................................................................................................................................................................

Bus Configuration Register.............................................................................................................................................................

Burst Length (BCR[2:0]) Default = Continuous Burst ................................................................................................................

Burst Wrap (BCR[3]) Default = No Wrap ...................................................................................................................................

Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ......................................................................................

WAIT Polarity (BCR[10]) Default = WAIT Active HIGH..............................................................................................................

Initial Access Latency (BCR[14]) Default = Variable..................................................................................................................

Operating Mode (BCR[15]) Default = Asynchronous Operation................................................................................................

Refresh Configuration Register......................................................................................................................................................

Device Identification Register.........................................................................................................................................................

Electrical Characteristics....................................................................................................................................................................

Timing Requirements..........................................................................................................................................................................

Timing Diagrams.................................................................................................................................................................................

Preliminary

EMC646SP16K

4Mx16 CellularRAM AD-MUX

List of Figures

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Functional Block Diagram - 4 Meg x 16 .............................................................................................................................

Power-Up Initialization Timing ...........................................................................................................................................

READ Operation ................................................................................................................................................................

WRITE Operation ..............................................................................................................................................................

Burst Mode READ(4-word burst)........................................................................................................................................

Burst Mode WRITE (4-word burst)......................................................................................................................................

Refresh Collision During Variable-Latency READ Operation .............................................................................................

Wired-OR WAIT Configuration ...........................................................................................................................................

Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ..........................................

Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ............................................

Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ..................................................................

Register READ, Synchronous Mode, Followed by READ ARRAY Operation ....................................................................

Load Configuration Register ..............................................................................................................................................

Read Configuration Register .............................................................................................................................................

Bus Configuration Register Definition ................................................................................................................................

WAIT Configuration During Burst Operation ......................................................................................................................

Latency Counter (Variable Initial Latency, No Refresh Collision) .......................................................................................

Latency Counter (Fixed Latency) .......................................................................................................................................

Refresh Configuration Register Mapping ...........................................................................................................................

AC Input / Output Reference Waveform ............................................................................................................................

AC Output Load Circuit ......................................................................................................................................................

Initialization Period ............................................................................................................................................................

Asynchronous READ .........................................................................................................................................................

Single-Access Burst READ Operation - Variable Latency .................................................................................................

4-Word Burst READ Operation - Variable Latency .............................................................................................................

Single-Access Burst READ Operation - Fixed Latency ......................................................................................................

4-Word Burst READ Operation - Fixed Latency .................................................................................................................

Burst READ Terminate at End-of-Row (Wrap off) ..............................................................................................................

Burst READ Row Boundary Crossing ................................................................................................................................

Asynchronous WRITE .......................................................................................................................................................

Burst WRITE Operation - Variable Latency Mode .............................................................................................................

Burst WRITE Operation - Fixed Latency Mode ..................................................................................................................

Burst WRITE Terminate at End-of-Row (Wrap off) ............................................................................................................

Burst WRITE Row Boundary Crossing ..............................................................................................................................

Burst WRITE Followed by Burst READ ..............................................................................................................................

Asynchronous WRITE Followed by Burst READ ...............................................................................................................

Burst READ Followed by Asynchronous WRITE ...............................................................................................................

Asynchronous WRITE Followed by Asynchronous READ .................................................................................................

Preliminary

EMC646SP16K

4Mx16 CellularRAM AD-MUX

List of Tables

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Signal Descriptions .........................................................................................................................................................

Bus Operations ...............................................................................................................................................................

Sequence and Burst Length ...........................................................................................................................................

Drive Strength .................................................................................................................................................................

Variable Latency Configuration Codes.............................................................................................................................

Fixed Latency Configuration Codes.................................................................................................................................

Address Patterns for PAR(RCR[4] =1).............................................................................................................................

Device Identification Register Mapping ...........................................................................................................................

Absolute Maximum Ratings ............................................................................................................................................

Electrical Characteristics and Operating Conditions .......................................................................................................

Capacitance ....................................................................................................................................................................

Asynchronous READ Cycle Timing Requirements .........................................................................................................

Burst READ Cycle Timing Requirements ........................................................................................................................

Asynchronous WRITE Cycle Timing Requirements ........................................................................................................

Burst WRITE Cycle Timing Requirements ......................................................................................................................

Initialization Timing Parameters ......................................................................................................................................

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