Z8523010PSC datasheet, PDF - EEWORLD Datasheet

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Z8523010PSC: DescriptionSerial I/O Controller, 2 Channel(s), 0.3125MBps, CMOS, PDIP40, PLASTIC, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，120 Pages; ManufacturerIXYS

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Z8523010PSC Overview

Serial I/O Controller, 2 Channel(s), 0.3125MBps, CMOS, PDIP40, PLASTIC, DIP-40

Z8523010PSC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IXYS
Parts packaging code	DIP
package instruction	PLASTIC, DIP-40
Contacts	40
Reach Compliance Code	unknown
Other features	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO
Address bus width	1
boundary scan	NO
maximum clock frequency	10 MHz
letter of agreement	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC
Data encoding/decoding methods	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.3125 MBps
External data bus width	8
JESD-30 code	R-PDIP-T40
JESD-609 code	e0
length	52.325 mm
low power mode	NO
Number of DMA channels
Number of I/O lines
Number of serial I/Os	2
Number of terminals	40
On-chip data RAM width
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Maximum seat height	4.24 mm
Maximum slew rate	12 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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Table of Contents

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pins Common to Both the Z85230 and Z80230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Descriptions Exclusive to the Z85230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Descriptions Exclusive to the Z80230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Input/Output Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ESCC Data Communications Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Z80230/Z85230 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-Byte Transmit FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-Byte Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write Register 7 PRIME (WR7’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CRC Reception in SDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TxD Forced High in SDLC with NRZI Encoding When Marking Idle . . . . . . . . . .

Improved Transmit Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DPLL Counter Tx Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Register 0 Status Latched During Read Cycle . . . . . . . . . . . . . . . . . . . . . . . .

Software Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fast SDLC Transmit Data Interrupt Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SDLC FIFO Frame Status Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FIFO Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FIFO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FIFO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SDLC Status FIFO Anti-Lock Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initializing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80230 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80230 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80230 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80230 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z85230 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z85230 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z85230 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z85230 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Z85230 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Z80230/Z85230 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IUS Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IUS Problem Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RTS Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RTS Problem Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Automatic TxD Forced High Problem Description . . . . . . . . . . . . . . . . . . . . . . . .

Automatic TxD Forced High Problem Solutions . . . . . . . . . . . . . . . . . . . . . . . . . .

SDLC FIFO Overflow Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SDLC FIFO Overflow Problem Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Default RR0 Value Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Default RR0 Value Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Default RR10 Value Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Default RR10 Value Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CRC Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CRC Problem Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

101

102

104

105

106

107

108

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z85230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z80230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

111

112

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List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Z85230 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Z80230 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Z85230 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Z80230 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ESCC Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ESCC Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ESCC Interrupt Priority Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Various ESCC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Detecting 5- or 7-Bit Synchronous Characters . . . . . . . . . . . . . . . . . . . . . . 17

SDLC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Write Register 7 Prime (WR7’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DMA Request on Transmit Deactivation Timing . . . . . . . . . . . . . . . . . . . . 25

TxIP Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DPLL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

SDLC Frame Status FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SDLC Byte Counting Detail 32

Z80230 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Z80230 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Z80230 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . 74

Read Cycle Timing (Z85230) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Write Cycle Timing (Z85230) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Interrupt Acknowledge Cycle Timing (Z85230) . . . . . . . . . . . . . . . . . . . . . 76

Standard and Open-Drain Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Z80230 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Z80230 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . 81

Z80230 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Z80230 General Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Z85230 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Z85230 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Z85230 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . 92

Z85230 Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Z85230 System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Z8523010PSC Related Products

	Z8523010PSC	Z8523008PSC	Z8523010PEC	Z8523016PEC	Z8023010PSC	Z8523020PSC	Z8523016PSC
Description	Serial I/O Controller, 2 Channel(s), 0.3125MBps, CMOS, PDIP40, PLASTIC, DIP-40	Serial I/O Controller, 2 Channel(s), 0.25MBps, CMOS, PDIP40, PLASTIC, DIP-40	Serial I/O Controller, 2 Channel(s), 0.3125MBps, CMOS, PDIP40, PLASTIC, DIP-40	Serial I/O Controller, 2 Channel(s), 0.512MBps, CMOS, PDIP40, PLASTIC, DIP-40	Serial I/O Controller, 2 Channel(s), 0.3125MBps, CMOS, PDIP40, PLASTIC, DIP-40	Serial I/O Controller, 2 Channel(s), 0.625MBps, CMOS, PDIP40, PLASTIC, DIP-40	Serial I/O Controller, 2 Channel(s), 0.512MBps, CMOS, PDIP40, PLASTIC, DIP-40
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	IXYS	IXYS	IXYS	IXYS	IXYS	IXYS	IXYS
Parts packaging code	DIP	DIP	DIP	DIP	DIP	DIP	DIP
package instruction	PLASTIC, DIP-40	PLASTIC, DIP-40	PLASTIC, DIP-40	PLASTIC, DIP-40	PLASTIC, DIP-40	PLASTIC, DIP-40	PLASTIC, DIP-40
Contacts	40	40	40	40	40	40	40
Reach Compliance Code	unknown	not_compliant	unknown	unknown	unknown	unknow	unknown
Address bus width	1	1	1	1	8	1	1
boundary scan	NO	NO	NO	NO	NO	NO	NO
maximum clock frequency	10 MHz	8 MHz	10 MHz	16 MHz	10 MHz	20 MHz	16 MHz
letter of agreement	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC	ASYNC, BIT; SYNC, HDLC; SYNC, SDLC; BISYNC
Data encoding/decoding methods	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)	NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.3125 MBps	0.25 MBps	0.3125 MBps	0.512 MBps	0.3125 MBps	0.625 MBps	0.512 MBps
External data bus width	8	8	8	8	8	8	8
JESD-30 code	R-PDIP-T40	R-PDIP-T40	R-PDIP-T40	R-PDIP-T40	R-PDIP-T40	R-PDIP-T40	R-PDIP-T40
JESD-609 code	e0	e0	e0	e0	e0	e0	e0
length	52.325 mm	52.325 mm	52.325 mm	52.325 mm	52.325 mm	52.325 mm	52.325 mm
low power mode	NO	NO	NO	NO	NO	NO	NO
Number of serial I/Os	2	2	2	2	2	2	2
Number of terminals	40	40	40	40	40	40	40
Maximum operating temperature	70 °C	70 °C	100 °C	100 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP	DIP	DIP	DIP	DIP
Encapsulate equivalent code	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6	DIP40,.6
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.24 mm	4.24 mm	4.24 mm	4.24 mm	4.24 mm	4.24 mm	4.24 mm
Maximum slew rate	12 mA	10 mA	12 mA	15 mA	12 mA	20 mA	15 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	15.24 mm	15.24 mm	15.24 mm	15.24 mm	15.24 mm	15.24 mm	15.24 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Other features	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO	-	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO	MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO

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