Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES
•
5 V tolerant inputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Complies with JEDEC standard no. 8-1A
•
Specified from
−40
to +85
°C
and from
−40
to +125
°C.
DESCRIPTION
74LVC00A
The 74LVC00A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74LVC00A provides the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE RANGE
74LVC00AD
74LVC00ADB
74LVC00APW
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PINS
14
14
14
PACKAGE
SO
SSOP
TSSOP
MATERIAL
plastic
plastic
plastic
CODE
SOT108-1
SOT337-1
SOT402-1
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
2.1
4.0
V
CC
= 3.3 V; notes 1 and 2 15
ns
pF
pF
UNIT
2002 Mar 05
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
handbook, halfpage
1
2
&
3
4
5
&
6
handbook, halfpage
A
Y
9
10
&
8
B
MNA211
12
13
&
11
MNA246
Fig.3 Logic symbol (IEEE/IEC).
Fig.4 Logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
PARAMETER
supply voltage
CONDITIONS
for maximum speed
performance
for low-voltage applications
V
I
V
O
T
amb
t
r
,t
f
input voltage
output voltage
operating ambient temperature
input rise and fall times
V
CC
= 1.2 to 2.7 V
V
CC
= 2.7 to 3.6 V
MIN.
2.7
1.2
0
0
−40
0
0
MAX.
3.6
3.6
5.5
V
CC
+125
20
10
V
V
V
V
°C
ns/V
ns/V
UNIT
2002 Mar 05
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LVC00A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
tot
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source or sink current
V
CC
or GND current
storage temperature
power dissipation per package
SO package
SSOP and TSSOP packages
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
above 70
°C
derate linearly with
8 mW/K
above 60
°C
derate linearly with
5.5 mW/K
−
−
500
500
mW
mW
V
I
< 0
note 1
V
O
> V
CC
or V
O
< 0
note 1
V
O
= 0 to V
CC
CONDITIONS
−
−0.5
−
−0.5
−
−
−65
MIN.
−0.5
MAX.
+6.5
−50
+6.5
±50
V
CC
+ 0.5
±50
±100
+150
V
mA
V
mA
V
mA
mA
°C
UNIT
2002 Mar 05
5
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