DSC2030
Low-Jitter Configurable LVDS Oscillator
General Description
The DSC2030 series of high performance
LVDS oscillators utilize a proven silicon MEMS
technology to provide excellent jitter and
stability while incorporating additional device
functionality. The DSC2030 allows the user
to easily modify the frequency of the
oscillator using pins.
The DSC2030 has
provision for up to four user-defined pre-
programmed,
pin-selectable
output
frequencies.
DSC2030 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Automotive.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
4 Pin-Selectable Output Frequencies
Short Lead Times: 2 Weeks
Wide Freq. Range:
o
LVDS Output: 2.3 to 460 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Consumer Electronics
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
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DSC2030
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MK-Q-B-P-D-12042606-2
DSC2030
Low-Jitter Configurable LVDS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
GND
FS0
FS1
NC
Output+
Output-
NC
NC
VDD2
VDD
NC
Pin Type
I
NA
NA
Power
I
I
NA
O
O
NA
NA
Power
Power
NA
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
Least significant bit for frequency selection
Most significant bit for frequency selection
Leave unconnected or grounded
Positive LVDS Output
Negative LVDS Output
Leave unconnected or grounded
Leave unconnected or grounded
Power Supply
Power Supply
Leave unconnected or grounded
Operational Description
The DSC2030 is a LVDS oscillator consisting of
a MEMS resonator and a support PLL IC. The
LVDS
output
is
generated
through
independent 8-bit programmable dividers from
the output of the internal PLL.
The actual frequency output by the DSC2030
is controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to four
different frequencies. Two control pins (FS0 –
FS1) select the output frequency. Discera
supports customer defined versions of the
DSC2030. Standard frequency options are
described in the following sections.
When Enable (pin 1) is floated or connected to
VDD, the DSC2030 is in operational mode.
Driving Enable to ground will tri-state output
driver (hi-impedance mode).
Output Clock Frequencies
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
C0001
C0002
C0003
C0004
C0005
C000X
Freq
(MHz)
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
Freq Select Bits [FS1, FS0] –
Default is [11]
00
148.35165
100
100
148.5
315
01
74.17582
0*
150
148.35
0*
10
148.5
0*
156.25
0*
0*
11
74.25
100
312.5
0*
315
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [11] and
the device will output the associated frequency highlighted in
Bold.
0* – denotes invalid selection, output frequency is not specified.
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DSC2030
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MK-Q-B-P-D-12042606-2
DSC2030
Low-Jitter Configurable LVDS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
40sec max.
DSC2030
F I 2
-
xxxxx
T
Freq (MHz)
See Freq. table
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output Offset Voltage
Delta Offset Voltage
(Unless specified otherwise: T=25° C)
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
40
1.125
350
200
2.3
48
2.5
0.28
0.4
1.7
350
460
52
1.4
50
Single-Ended
4
Min.
2.25
Typ.
21
29
Max.
3.6
23
32
±10
±25
±50
±5
5
Unit
V
mA
mA
ppm
ppm
ms
V
ns
ns
kΩ
V
mV
mV
ps
MHz
%
ps
RMS
ps
RMS
EN pin low – output is disabled
EN pin high – outputs are enabled
R
L
=100Ω, F
O
= 156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
-
0.25xV
DD
5
20
LVDS Output
R=100Ω Differential
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
t
R
t
F
f
0
SYM
J
PER
J
CC
20% to 80%
R
L
=100Ω, C
L
= 2pF
Single Frequency
Differential
F
O
=156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2030
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MK-Q-B-P-D-12042606-2
DSC2030
Low-Jitter Configurable LVDS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
156MHz-LVDS
Phase Jitter (ps RMS)
2.0
212MHz-LVDS
320MHz-LVDS
1.5
410MHz-LVDS
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
LVDS Phase jitter (integrated phase noise)
Output Waveform: LVDS
t
R
t
F
Output
Output
80
%
50%
20%
350
mv
830
mV
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
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DSC2030
Page 4
MK-Q-B-P-D-12042606-2
DSC2030
Low-Jitter Configurable LVDS Oscillator
Solder Reflow Profile
cM
ax
260
°
C
.
20-40
Sec
217
°
C
200
°
C
.
ax
60-150
Sec
150
°
C
3C
/S e
60-180
Sec
cM
Reflow
Pre heat
8 min max
Cool
Time
25
°
C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
255-260°C
Peak Temperature
Time within 5°C of actual Peak
20-40 Sec
6°C/Sec Max.
Ramp-Down Rate
Time 25°C to Peak Temperature
8 min Max.
Temperature (°C)
3C
/
Se
/
/S
6C/
e
e
ec
x
x
x.
Ma
Package Dimensions
3.2 x 2.5 mm 14 Lead Plastic Package
Disclaimer:
Discera makes no warranty of any kind, express or implied, with regard to this material,
including, but not limited to, the implied warranties of merchantability and fitness for a
particular purpose. Discera reserves the right to make changes without further notice to
materials described herein. Discera does not assume any liability arising from the
application or use of any product or circuit described herein. Discera does not authorize its
products for use a critical components in life-support systems where a malfunction or
failure may reasonably be expected to result in significant injury to the user. The inclusion
of Discera’s product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Discera against all charges.
DISCERA, Inc.
●
Phone: +1 (408) 432-8600
1961 Concourse Drive,
San Jose, California
95131
●
Fax: +1 (408) 432-8609 ● Email: sales@discera.com
●
●
USA
www.discera.com
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DSC2030
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MK-Q-B-P-D-12042606-2
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