All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 1
DSC2033
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
GND
FS0
FS1
FS2
Output1+
Output1-
Output 2-
Output 2+
VDD2
VDD
NC
Pin
Type
I
NA
NA
Power
I
I
I
O
O
O
O
Power
Power
NA
Low-Jitter Pin-Configurable Dual LVDS Oscillator
Description
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVDS Output 1
Negative LVDS Output 1
Negative LVDS Output 2
Positive LVDS Output 2
Power Supply 2 for LVDS Output 2
Power Supply
Leave unconnected or grounded
General Description
The DSC2033 is a dual output LVDS oscillator
consisting of a MEMS resonator and a support
PLL IC.
The two outputs are generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
Two constraints are imposed on the output
frequencies: 1) f
2
=M x f
1
/N, where M and N
are even integers between 4 and 254, 2)
1.2GHz < N x f
2
< 1.7GHz.
The actual frequencies output by the DSC2033
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2033.
Standard frequency options are described in in
the following sections.
When Enable (pin 1) is floated or connected to
VDD, the DSC2033 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
Output Frequency Combinations
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code above. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
A0001
A0002
Freq
(MHz)
f
OUT1
f
OUT2
f
OUT1
f
OUT2
Freq Select Bits [FS2, FS1, FS0] –
Default is [111]
000
74.25
33
001
156.25
125
010
150
125
011
125
25
100
125
50
101
100
50
110
100
75
111
400
200
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and
the device will output the associated frequency highlighted in
Bold.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 2
DSC2033
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Low-Jitter Pin-Configurable Dual LVDS Oscillator
Ordering Code
Unit
V
V
°C
°C
°C
V
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Conditio
n
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
DSC2033
C I 2
40sec max.
Package
C: 3.2x2.5mm
-
xxxxx
T
Freq (MHz)
See Freq. table
Stability
1: ±50ppm
2: ±25ppm
4: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
(Unless specified otherwise: T=25° C)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Spurious Frequencies
6
Notes:
1.
2.
3.
4.
5.
6.
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
Spurious frequencies include crosstalk from adjacent output within 20 MHz of the output clock frequency.
4
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
EN pin low – outputs are disabled
EN pin high – outputs are enabled
LVDS: R
L
=100Ω, F
0
=156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
Min.
2.25
Typ.
21
38
Max.
3.6
26
Unit
V
mA
mA
±10
±25
±50
±5
10
0.75xV
DD
-
-
0.25xV
DD
100
5
33
1.125
350
300
10
48
3.3
0.43
0.55
1.8
-50
425
52
1.4
50
ppm
ppm
ms
V
ns
us
kΩ
V
mV
mV
ps
MHz
%
ps
RMS
ps
RMS
dBc
LVDS Outputs
R=100Ω Differential
Single-Ended
t
R
t
F
f
0
SYM
J
PER
J
CC
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
F
01
= 156.25 MHz
F
02
= 156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
3
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 3
DSC2033
Low-Jitter Pin-Configurable Dual LVDS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
156MHz-LVDS
Phase Jitter (ps RMS)
2.0
212MHz-LVDS
320MHz-LVDS
1.5
410MHz-LVDS
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
LVDS Phase jitter (integrated phase noise)
LVDS Output Waveform
t
R
t
F
Output
Output
80
%
50%
20%
350 mV
830 mv
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
Solder Reflow Profile
cM
ax
260
°
C
.
20-40
Sec
217
°
C
200
°
C
.
ax
60-150
Sec
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
Pre heat
8 min max
Cool
Time
25
°
C
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
255-260°C
Peak Temperature
Time within 5°C of actual Peak
20-40 Sec
6°C/Sec Max.
Ramp-Down Rate
Time 25°C to Peak Temperature
8 min Max.
Temperature (°C)
3C
/
Se
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Page 4
/
/S
6C/
e
e
ec
Ma
x
x
x.
DSC2033
Package Dimensions
Low-Jitter Pin-Configurable Dual LVDS Oscillator
3.2 x 2.5 mm Plastic Package
Recommended
Solder Pad Layout
units: mm[inch]
2.60
1.90
0.50
0.25
0.50
DISCERA, Inc.
●
Phone: +1 (408) 432-8600
1961 Concourse Drive,
San Jose, California
95131
●
Fax: +1 (408) 432-8609 ● Email: sales@discera.com
●
●
USA
www.discera.com
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
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