L-FW323-07-NV129-DT datasheet, PDF

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L-FW323-07-NV129-DT: DescriptionSerial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA129, ROHS COMPLIANT, VTFSBGAC-129; CategoryThe embedded processor and controller Microcontrollers and processors; File Size932KB，80 Pages; ManufacturerBroadcom; Environmental Compliance

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L-FW323-07-NV129-DT Overview

Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA129, ROHS COMPLIANT, VTFSBGAC-129

L-FW323-07-NV129-DT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Broadcom
package instruction	VFBGA, BGA129,13X13,20
Reach Compliance Code	compliant
Address bus width
boundary scan	NO
maximum clock frequency	24.578 MHz
letter of agreement	ASYNC, BIT
Maximum data transfer rate	50 MBps
External data bus width
JESD-30 code	S-PBGA-B129
JESD-609 code	e1
length	7 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	129
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA129,13X13,20
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	0.98 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	7 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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Data Sheet

September 2006

™

FW323 07 NV129 1394a

PCI PHY/Link Open Host Controller Interface

1 Features

129-ball VTFSBGA lead-free package.

1394a-2000 OHCI link and PHY core function in a

single device:

— Single-chip link and PHY enable smaller, sim-

pler, more efficient motherboard and add-in card

designs.

— Compatibility with current

Microsoft Windows

drivers and common applications.

— Interoperability with existing, as well as older,

1394 consumer electronics and peripherals

products.

— Support low-power system designs (CMOS

implementation and power management fea-

tures).

— LPS, LKON, and CNA outputs to support legacy

power management implementations.

OHCI:

— Complies with the

1394 OHCI 1.1 Specification.

— OHCI 1.0 backwards compatible: configurable

via PCI bus commands to operate in either

OHCI 1.0 or OHCI 1.1 mode.

— Listed on

Windows

hardware compatibility list

http://testedproducts.windowsmarketplace.com/.

— Compatible with

Microsoft Windows

and

MacOS

operating systems.

— 4 Kbyte isochronous transmit FIFO.

— 2 Kbyte asynchronous transmit FIFO.

— 4 Kbyte isochronous receive FIFO.

— 2 Kbyte asynchronous receive FIFO.

— Dedicated asynchronous and isochronous

descriptor-based DMA engines.

— Eight isochronous transmit/receive contexts.

— Prefetches isochronous transmit data.

— Supports posted write transactions.

— Supports parallel processing of incoming physi-

cal read and write requests.

— May be used without an EEPROM when the

system BIOS is programmed with the EEPROM

contents.

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000, Standard

for a High Performance Serial Bus.

— Provides three fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic.

— Does not require external filter capacitor for

PLL.

— Supports link-on as a part of the internal

PHY core-link interface.

— Supports arbitrated short bus reset to improve

utilization of the bus.

— Supports multispeed packet concatenation.

— Supports PHY pinging and remote PHY access

packets.

— Reports cable power fail interrupt when voltage

at CPS pin falls below 7.5 V.

PCI:

— Revision 2.3 compliant.

— 33 MHz/32-bit operation.

— Programmable burst size thresholds for PCI

data transfer.

— Supports optimized memory read line, memory

read multiple, and memory write invalidate burst

commands.

— Supports

PCI Bus Power Management Interface

Specification

v.1.1.

— Supports CLKRUN# protocol per PCI Mobile

Design Guide.

— Supports

Mini PCI Specification

v1.0, including

Mini PCI

power requirements.

— CardBus support per PC card standard

release 8.0, including 128 bytes of on-chip tuple

memory.

1.1 Other Features

CMOS process

3.3 V operation, 5 V tolerant inputs

C serial ROM interface

FW323 07 NV129 1394a

PCI PHY/Link Open Host Controller Interface

Data Sheet

September 2006

Table of Contents

Contents

Page

1 Features ....................................................................................................................................................................... 1

1.1 Other Features ................................................................................................................................................... 1

2 FW323 07 NV129 Functional Overview ....................................................................................................................... 7

3 FW323 07 NV129 Functional Description .................................................................................................................... 7

3.1 PCI Core ............................................................................................................................................................ 8

3.2 OHCI Data Transfer ........................................................................................................................................... 9

3.3 OHCI Isochronous Data Transfer ...................................................................................................................... 9

3.4 Isochronous Register Access ............................................................................................................................ 9

3.5 OHCI Asynchronous Data Transfer ................................................................................................................. 10

3.6 Asynchronous Register Access ....................................................................................................................... 10

3.7 Link Core .......................................................................................................................................................... 12

3.8 PHY/Link Interface ........................................................................................................................................... 14

3.9 PHY Core ......................................................................................................................................................... 14

4 Ball Information .......................................................................................................................................................... 16

5 Internal Registers ....................................................................................................................................................... 22

5.1 PCI Configuration Registers ............................................................................................................................ 22

5.2 Vendor ID Register .......................................................................................................................................... 23

5.3 Device ID Register ........................................................................................................................................... 23

5.4 PCI Command Register ................................................................................................................................... 24

5.5 PCI Status Register ......................................................................................................................................... 25

5.6 Class Code and Revision ID Registers ............................................................................................................ 26

5.7 Latency Timer and Cache Line Size Register .................................................................................................. 26

5.8 Header Type and BIST Register ...................................................................................................................... 27

5.9 OHCI Base Address Register .......................................................................................................................... 27

5.10 PCI Subsystem Identification Register ........................................................................................................... 28

5.11 PCI Power Management Capabilities Pointer Register ................................................................................. 28

5.12 Interrupt Line and Pin Register ...................................................................................................................... 28

5.13 MIN_GNT and MAX_LAT Register ................................................................................................................ 29

5.14 PCI OHCI Control Register ............................................................................................................................ 29

5.15 Capability ID and Next Item Pointer Register ................................................................................................ 30

5.16 Power Management Capabilities Register ..................................................................................................... 31

5.17 Power Management Control and Status Register .......................................................................................... 32

5.18 Power Management CSR PCI-to-PCI Bridge Support Extensions ................................................................ 33

5.19 Power Management Data .............................................................................................................................. 33

5.20 OHCI Registers .............................................................................................................................................. 34

5.21 OHCI Version Register .................................................................................................................................. 37

5.22 Asynchronous Transmit Retries Register ...................................................................................................... 37

5.23 CSR Data Register ........................................................................................................................................ 38

5.24 CSR Compare Register ................................................................................................................................. 38

5.25 CSR Control Register .................................................................................................................................... 38

5.26 Configuration ROM Header Register ............................................................................................................. 39

5.27 Bus Identification Register ............................................................................................................................. 39

5.28 Bus Options Register ..................................................................................................................................... 40

5.29 GUID High Register ....................................................................................................................................... 40

5.30 GUID Low Register ........................................................................................................................................ 41

5.31 Configuration ROM Mapping Register ........................................................................................................... 41

5.32 Posted Write Address Low Register .............................................................................................................. 41

5.33 Posted Write Address High Register ............................................................................................................. 42

5.34 Vendor ID Register ........................................................................................................................................ 42

5.35 Host Controller Control Register .................................................................................................................... 42

5.36 SelfID Buffer Pointer Register ........................................................................................................................ 44

5.37 SelfID Count Register .................................................................................................................................... 44

5.38 Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register ...................................... 45

5.39 Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register ...................................... 45

Agere Systems Inc.

Data Sheet

September 2006

FW323 07 NV129 1394a

PCI PHY/Link Open Host Controller Interface

Table of Contents

(continued)

Contents

Page

5.40 Interrupt Event (IntEvent) Register ................................................................................................................. 45

5.41 Interrupt Mask (IntMask) Register .................................................................................................................. 48

5.42 Isochronous Transmit Interrupt Event (isoXmitIntMask) Register .................................................................. 49

5.43 Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register ................................................................... 50

5.44 Isochronous Receive Interrupt Event (isoRecvIntEvent) Register ................................................................. 50

5.45 Isochronous Receive Interrupt Mask (isoRecvIntMask) Register ................................................................... 51

5.46 Fairness Control Register ............................................................................................................................... 51

5.47 Link Control Register ...................................................................................................................................... 52

5.48 Node Identification Register ........................................................................................................................... 53

5.49 PHY Core Layer Control Register .................................................................................................................. 54

5.50 Isochronous Cycle Timer Register ................................................................................................................. 54

5.51 Asynchronous Request Filter High Register .................................................................................................. 55

5.52 Asynchronous Request Filter Low Register ................................................................................................... 55

5.53 Physical Request Filter High Register ............................................................................................................ 56

5.54 Physical Request Filter Low Register ............................................................................................................. 56

5.55 Asynchronous Context Control Register ........................................................................................................ 57

5.56 Asynchronous Context Command Pointer Register ....................................................................................... 58

5.57 Isochronous Transmit Context Control (IT DMA ContextControl) Register .................................................... 58

5.58 Isochronous Transmit Context Command Pointer Register ........................................................................... 59

5.59 Isochronous Receive Context Control (IR DMA ContextControl) Register .................................................... 60

5.60 Isochronous Receive Context Command Pointer Register ............................................................................ 61

5.61 Isochronous Receive Context Match (IR DMA ContextMatch) Register ........................................................ 62

5.62 FW323 Vendor-Specific Registers ................................................................................................................. 63

5.63 Isochronous DMA Control .............................................................................................................................. 63

5.64 Asynchronous DMA Control ........................................................................................................................... 64

5.65 Link Options ................................................................................................................................................... 65

6 Internal Register Configuration .................................................................................................................................. 66

6.1 PHY Core Register Map ................................................................................................................................... 66

6.2 PHY Core Register Fields ................................................................................................................................ 66

7 Crystal Selection Considerations ............................................................................................................................... 70

7.1 Load Capacitance ............................................................................................................................................ 70

7.2 Adjustment to Crystal Loading ......................................................................................................................... 71

7.3 Crystal/Board Layout ........................................................................................................................................ 71

8 NAND Tree Testing .................................................................................................................................................... 71

9 Solder Reflow and Handling ....................................................................................................................................... 74

10 Absolute Maximum Voltage/Temperature Ratings ................................................................................................... 74

11 Electrical Characteristics .......................................................................................................................................... 75

12 Timing Characteristics .............................................................................................................................................. 77

13 Outline Diagram ....................................................................................................................................................... 78

13.4 129-Ball VTFSBGAC ...................................................................................................................................... 78

14 Ordering Information ................................................................................................................................................ 79

Agere Systems Inc.

Data Sheet

September 2006

FW323 07 NV129 1394a

PCI PHY/Link Open Host Controller Interface

List of Tables

Table

Page

Table 1. Cable Ports ..............................................................................................................................................17

Table 2. PCI Signals ..............................................................................................................................................18

Table 3. Test, Reset, Clock, and Configuration Signals .........................................................................................19

Table 4. Power Signals ..........................................................................................................................................21

Table 5. Bit-Field Access Tag Description .............................................................................................................22

Table 6. PCI Configuration Register Map ..............................................................................................................22

Table 7. PCI Command Register Description ........................................................................................................24

Table 8. PCI Status Register ..................................................................................................................................25

Table 9. Class Code and Revision ID Register Description ...................................................................................26

Table 10. Latency Timer and Class Cache Line Size Register Description ...........................................................26

Table 11. Header Type and BIST Register Description .........................................................................................27

Table 12. OHCI Base Address Register Description .............................................................................................27

Table 13. PCI Subsystem Identification Register Description ................................................................................28

Table 14. Interrupt Line and Pin Register Description ...........................................................................................28

Table 15. MIN_GNT and MAX_LAT Register Description .....................................................................................29

Table 16. PCI OHCI Control Register Description .................................................................................................29

Table 17. Capability ID and Next Item Pointer Register Description ......................................................................30

Table 18. Power Management Capabilities Register Description ..........................................................................31

Table 19. Power Management Control and Status Register Description ...............................................................32

Table 20. Power Management Data Register Description .....................................................................................33

Table 21. OHCI Register Map ................................................................................................................................34

Table 22. OHCI Version Register Description ........................................................................................................37

Table 23. Asynchronous Transmit Retries Register Description ............................................................................37

Table 24. CSR Data Register Description ..............................................................................................................38

Table 25. CSR Compare Register Description ......................................................................................................38

Table 26. CSR Control Register Description ..........................................................................................................38

Table 27. Configuration ROM Header Register Description ..................................................................................39

Table 28. Bus Identification Register Description ..................................................................................................39

Table 29. Bus Options Register Description ..........................................................................................................40

Table 30. GUID High Register Description ............................................................................................................40

Table 31. GUID Low Register Description .............................................................................................................41

Table 32. Configuration ROM Mapping Register Description ................................................................................41

Table 33. Posted Write Address Low Register Description ...................................................................................41

Table 34. Posted Write Address High Register Description ...................................................................................42

Table 35. Vendor ID Register Description ..............................................................................................................42

Table 36. Host Controller Control Register Description .........................................................................................42

Table 37. SelfID Buffer Pointer Register Description .............................................................................................44

Table 38. SelfID Count Register Description .........................................................................................................44

Table 39. Isochronous Receive Channel Mask High Register Description ............................................................45

Table 40. Isochronous Receive Channel Mask Low Register Description .............................................................45

Table 41. Interrupt Event Register Description ......................................................................................................46

Table 42. Interrupt Mask Register Description .......................................................................................................48

Table 43. Isochronous Transmit Interrupt Event Register Description ...................................................................49

Table 44. Isochronous Transmit Interrupt Event Description .................................................................................50

Table 45. Isochronous Receive Interrupt Event Description ..................................................................................50

Table 46. Fairness Control Register Description ...................................................................................................51

Table 47. Link Control Register Description ...........................................................................................................52

Table 48. Node Identification Register Description ................................................................................................53

Table 49. PHY Core Layer Control Register Description .......................................................................................54

Table 50. Isochronous Cycle Timer Register Description ......................................................................................54

Table 51. Asynchronous Request Filter High Register Description .......................................................................55

Agere Systems Inc.

L-FW323-07-NV129-DT Related Products

	L-FW323-07-NV129-DT	L-FW323-07-NV129-DB
Description	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA129, ROHS COMPLIANT, VTFSBGAC-129	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA129, ROHS COMPLIANT, VTFSBGAC-129
Is it Rohs certified?	conform to	conform to
Maker	Broadcom	Broadcom
package instruction	VFBGA, BGA129,13X13,20	VFBGA, BGA129,13X13,20
Reach Compliance Code	compliant	compliant
boundary scan	NO	NO
maximum clock frequency	24.578 MHz	24.578 MHz
letter of agreement	ASYNC, BIT	ASYNC, BIT
Maximum data transfer rate	50 MBps	50 MBps
JESD-30 code	S-PBGA-B129	S-PBGA-B129
JESD-609 code	e1	e1
length	7 mm	7 mm
low power mode	YES	YES
Number of serial I/Os	2	2
Number of terminals	129	129
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA
Encapsulate equivalent code	BGA129,13X13,20	BGA129,13X13,20
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	0.98 mm	0.98 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	BALL
Terminal pitch	0.5 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40
width	7 mm	7 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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