EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Features
!
!
!
!
!
!
!
!
!
!
!
!
!
Programmable PLL synthesizer
8-channel preconfigured or fully programmable SPI mode
Double super-heterodyne receiver architecture with 2
nd
mixer as image rejection mixer
Reception of FSK, FM and ASK modulated signals
Low shut-down and operating currents
Build-in acceptance of input frequency variations
On-chip IF filter
Fully integrated FSK/FM demodulator
RSSI for level indication and ASK detection
2
nd
order low-pass data filter
Positive and negative peak detectors
Data slicer (with averaging or peak-detector adaptive threshold)
EVB programming software is available on Melexis web site
Ordering Information
Part No. (see paragraph 6)
EVB71122C-315-C
EVB71122C-433-C
Note:
SPI mode is default population, ABC mode according to paragraph 4.2
Application Examples
!
General digital and analog RF receivers
at 300 to 930MHz
!
Tire pressure monitoring systems (TPMS)
!
Remote keyless entry (RKE)
!
Low power telemetry systems
!
Alarm and security systems
!
Active RFID tags
!
Remote controls
!
Garage door openers
!
Home and building automation
Y
R
A
IN
IM
L
E
R
P
EVB71122C-868-C
EVB71122C-915-C
Evaluation Board Example
General Description
The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architec-
ture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels
or frequency programmable via a 3-wire serial programming interface (SPI).
The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz
or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz.
39012 71122 01
Rev. 001
Page 1 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Document Content
1
Theory of Operation ...................................................................................................4
1.1
1.2
1.3
1.4
1.5
1.6
1.7
General............................................................................................................................. 4
EVB Data Overview .......................................................................................................... 4
Block Diagram .................................................................................................................. 5
Enable/Disable in ABC Mode ........................................................................................... 6
Demodulation Selection in ABC Mode.............................................................................. 6
Programming Modes ........................................................................................................ 6
Preconfigured Frequencies in ABC Mode ........................................................................ 6
2
Functional Description ..............................................................................................7
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Frequency Planning.......................................................................................................... 7
Calculation of Counter Settings ........................................................................................ 8
Calculation of LO1 and IF1 frequency for Low Frequency Bands............................................... 8
Calculation of LO1 and IF1 frequency for High Frequency Bands.............................................. 9
Counter Setting Examples for SPI Mode ..................................................................................... 9
Counter Settings in ABC Mode – 8 Preconfigured Channels.................................................... 10
PLL Counter Ranges ................................................................................................................. 11
2.3
2.3.1
2.3.2
2.3.3
SPI Description............................................................................................................... 11
General ...................................................................................................................................... 11
Read / Write Sequences............................................................................................................ 12
Serial Programming Interface Timing ........................................................................................ 12
3
Register Description ................................................................................................13
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
Register Overview .......................................................................................................... 13
Control Word R0 ........................................................................................................................ 15
Control Word R1 ........................................................................................................................ 16
Control Word R2 ........................................................................................................................ 17
Control Word R3 ........................................................................................................................ 17
Control Word R4 ........................................................................................................................ 18
Control Word R5 ........................................................................................................................ 18
Control Word R6 ........................................................................................................................ 18
Control Word R7 (Read-only Register)...................................................................................... 19
Y
R
A
IN
IM
L
E
R
P
4
Application Circuits .................................................................................................20
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Standard FSK & ASK Circuit in SPI Mode...................................................................... 20
Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 20
Component Arrangement Top Side for SPI Mode (Averaging Data Slicer) .............................. 21
Peak Detector Data Slicer Configured for NRZ Codes ............................................................. 22
Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)........................ 23
Board Component Values List (SPI mode)................................................................................ 24
39012 71122 01
Rev. 001
Page 2 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2
4.2.1
4.2.2
4.2.3
Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode.......................... 25
Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 25
Component Arrangement Top Side for ABC Mode (averaging data slicer) .............................. 26
Board Component Values List (ABC mode) .............................................................................. 27
5
6
7
Evaluation Board Layouts .......................................................................................28
Board Variants..........................................................................................................28
Package Description ................................................................................................29
7.1
Soldering Information ..................................................................................................... 29
8
9
10
Reliability Information .............................................................................................30
ESD Precautions ......................................................................................................30
Disclaimer .................................................................................................................32
Y
R
A
IN
IM
L
E
R
P
39012 71122 01
Rev. 001
Page 3 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1
1.1
Theory of Operation
General
The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator
with external inductor, a programmable feedback divider chain, a programmable reference divider, a phase-
frequency detector with a charge pump and an external loop filter.
In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator
signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermedi-
ate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is
provided even without using an RF front-end filter. At applications asking for very high image rejections,
cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.
The receiver signal chain is setup by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and
MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an
FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based
ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator.
The data slicer threshold can be generated from the mean-value of the data stream or by means of the posi-
tive and negative peak detectors (PKDET+/-).
In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned
off, and to several other operating modes. There are two global operating modes that are selectable via the
logic level at pin SPISEL:
•
•
8-channel preconfigured mode (ABC
mode)
fully programmable mode (SPI
mode).
In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is
required. In this case the three lines of the serial programming interface (SPI) are used to select one of the
eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are
used to enable/disable the receiver and to select FSK or ASK demodulation, respectively.
SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are config-
ured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the
receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types,
data slicer settings and more. The pin MODSEL has no effect in this mode.
Y
R
A
IN
IM
L
E
R
P
-3
1.2
!
!
!
!
!
!
!
EVB Data Overview
!
Total image rejection: > 65dB (with external
RF front-end filter)
!
FSK/FM deviation range: ±10 to ±50kHz
!
Spurious emission: < -70dBm
!
Linear RSSI range: > 70dB
!
FSK input frequency acceptance range:
170kHz (3dB)
!
Crystal reference frequency: 10MHz
Input frequency ranges: 300 to 930MHz
Power supply range: 3.0 to 5.5V
Temperature range: -40 to +105°C
Shutdown current: 50nA
Operating current: 11mA (typ.)
Internal IF2: 2MHz with 230kHz 3dB bandwidth
Maximum data rate: 100kbps NRZ code,
50kbps bi-phase code
!
Minimum frequency resolution: 10kHz
!
Input Sensitivity: at 4 kbps NRZ, BER = 3·10
Frequency
FSK:
±20 kHz deviation
ASK
315 MHZ
-106dBm
-108dBm
433 MHz
-104dBm
-108dBm
868 MHz
-101dBm
-106dBm
915 MHz
-101dBm
-106dBm
39012 71122 01
Rev. 001
Page 4 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1.3
Block Diagram
LNAO
VEELNA
VCCANA
RSSI
3
4
8
9
MODSEL
DF2
2
VEEIF
6
MIXP
5
MIXN
DF1
1
28
200k
29
200k
ASK
OA1
DFO
27
MIX1
LNAI
31
200k
1M
LNA
LO1
IF1
MIX2
IF2
IFF
IFA
FSK
SW1
PKDET+
25
LO2
FSK
DEMOD
1M
PDP
LO2DIV
N/A
counter
VCO
LF
VCCVCO
VEEVCO
MFO
PKDET_
PDN
26
PFD
R
counter
Control
Logic
C/SDEN
B/SDTA
SPISEL
A/SCLK
SLCSEL
SW2
CP
RO
BIAS
VEEANA
VCCDIG
VEEDIG
OA2
DTAO
22
SLC
RBIAS
32
11
14
TNK1
12 13
TNK2
15
23
24
7
17
18
19
10
16
ENRX
ROI
LF
20
21
30
Fig. 1:
MLX71122 block diagram
The MLX71122 receiver IC consists of the following building blocks:
•
•
•
•
•
•
•
•
•
•
•
•
PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,
parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,
the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator
(RO)
Low-noise amplifier (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth
IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detector data slicer
Control logic with 3-wire bus serial programming interface (SPI)
Biasing circuit with modes control
Y
R
A
IN
IM
L
E
R
P
For more detailed information, please refer to the latest MLX71122 data sheet revision.
39012 71122 01
Rev. 001
Page 5 of 32
EVB Description
Sept/06
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
