v3.2
eX Automotive Family FPGAs
u e
™
Specifications
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22
µm
CMOS Process Technology
Up to 132 User-Programmable I/O Pins
•
•
•
•
•
Features
•
•
•
•
•
•
•
250 MHz Internal Performance, Low-Power Antifuse
FPGA
Advanced Small-Footprint Packages
Pin-to-Pin Compatibility with eX Commercial- and
Industrial-Grade Devices
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
Live on Power-Up
•
•
•
•
•
No Power-Up/Down Sequence Required for Supply
Voltages
Configurable Weak Resistor Pull-Up or Pull-Down
for Tristated Outputs during Power-Up
Individual Output Slew-Rate Control
2.5 V and 3.3 V I/Os
Software Design Support with Actel Designer and
Libero
®
Integrated Design Environment (IDE)
Tools
Up to 100% Resource Utilization with 100% Pin
Locking
Deterministic Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
FuseLock™ Secure Programming Technology
Prevents Reverse Engineering and Design Theft
Product Profile
Device
Capacity
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Combinatorial Cells
Maximum User I/Os
Global Clocks
Hardwired
Routed
Speed Grades*
Temperature Grades*
Package
(by pin count)
TQFP
CSP
eX64
3,000
2,000
64
128
128
84
1
2
Std.
A
64, 100
49, 128
eX128
6,000
4,000
128
256
256
100
1
2
Std.
A
64, 100
49, 128
eX256
12,000
8,000
256
512
512
132
1
2
Std.
A
100
128, 180
Note:
* The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to the
eX
Family FPGAs
datasheet for more details.
June 2006
© 2006 Actel Corporation
i
eX Automotive Family FPGAs
Ordering Information
eX128
TQ
G
100
A
Application (Ambient Temperature Range)
A = Automotive (-40˚C to 125˚C)
Blank = Commercial (0˚C to 70˚C)
I = Industrial (-40˚C to 85˚C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
TQ = Thin Quad Flat Pack (1.4mm pitch)
CS = Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank= Standard Speed
P = Approximately 30% Faster than Standard
F = Approximately 40% Slower than Standard
Part Number
eX64 = 64 Dedicated Flip-Flops (3,000 System Gates)
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Note:
Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on
characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to
ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing
options available.
Plastic Device Resources
User I/Os (Including Clock Buffers)
Device
eX64
eX128
eX256
64-Pin TQFP
41
46
—
100-Pin TQFP
56
70
81
49-Pin CSP
36
36
—
128-Pin CSP
84
100
100
180-Pin CSP
—
—
132
Note: Package Definitions:
TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
Speed Grade and Temperature Grade Matrix
Std.
A
✓
Note:
Refer to the
eX Family FPGAs
datasheet for more details on commercial-
and industrial-grade offerings.
Contact your local Actel representative for device availability.
ii
v3.2
eX Automotive Family FPGAs
Table of Contents
eX Automotive Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.5 V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
CEQ Values for eX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Package Pin Assignments
64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
49-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
128-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
This datasheet version contains information that is considered to be final. . . . . . 3-1
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v3.2
iii
eX Automotive Family FPGAs
eX Automotive Family FPGAs
General Description
Based on a 0.22 µm CMOS process technology, the eX
family of FPGAs is a low-cost solution for low-power,
high-performance designs. With the automotive
temperature grade support (–40ºC to 125ºC), the eX
devices can address many in-cabin telematics and
automobile interconnect applications. The low-power
attributes inherent in antifuse technology make the eX
devices ideal for designers who are looking to integrate
low-density, power-sensitive automotive applications
into a programmable logic solution, enabling quick time-
to-market.
low-signal impedance. The antifuses are normally open
circuit and, when programmed, form a permanent low-
impedance connection. Actel’s eX family provides two
types of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure
1-1).
The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the eX FPGA. The clock source for the R-
cell can be chosen from either the hardwired clock or the
routed clock.
The C-cell implements a range of combinatorial functions
up to five inputs (Figure
1-2 on page 1-2).
Inclusion of
the DB input and its associated inverter function enables
the implementation of more than 4,000 combinatorial
functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-
flop to imitate an R-cell via the use of the CC macro. This
is particularly useful when implementing nontiming-
critical paths and when the design engineer is running
out of R-cells. For more information about the CC macro,
refer to the Actel
Maximizing Logic Utilization in eX, SX
and SX-A FPGA Devices Using CC Macros
application
note.
eX Family Architecture
The Actel eX family is implemented on a high-voltage
twin-well CMOS process using 0.22 µm design rules. The
eX family architecture uses a “sea-of-modules” structure
where the entire floor of the device is covered with a
grid of logic modules with virtually no chip area lost to
interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
patented
metal-to-metal
programmable
antifuse
interconnect elements. The antifuse interconnect is
made up of a combination of amorphous silicon and
dielectric material with barrier metals and has an "on"
state resistance of 25
Ω
with a capacitance of 1.0 fF for
S0
Routed
Data Input S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CKS
Figure 1-1 •
R-Cell
CLR
CKP
v3.2
1-1
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